HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 77

• Manufacturer Part Number: HC230
• Description: HardCopy II Device Family
• Manufacturer: ALTERA [Altera Corporation]

HighSpeed I/O
Specifications
Altera Corporation
September 2008
Notes to
(1)
(2)
(3)
(4)
Differential
SSTL-2 Class I
(3)
Differential
SSTL-2 Class II
(3)
Differential
SSTL-18 Class I
(3)
Differential
SSTL-18 Class II
(3)
1.8-V Differential
HSTL Class I
1.8-V Differential
HSTL Class II
1.5-V Differential
HSTL Class I
t
f
J
C
HSCLK
Table 4–38. HardCopy II Maximum Output Clock Rate for HC210W using OCT
Table 4–39. HighSpeed Timing Specifications and Definitions (Part 1 of 2)
HighSpeed Timing Specifications
I/O Standard
The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology
on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from
0 to 5 pF.
CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and excluded from this table.
Like Stratix II devices, differential HSTL and SSTL is supported only on the column CLK, PLL_OUT and memory
interface DQS IOE pins. For HC210 and HC220, only the top column clock pins support differential HSTL and SSTL.
These numbers are preliminary and pending further silicon characterization.
Table
(3)
(3)
(3)
4–38:
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
Strength
Drive
Table 4–39
Interface
Memory
IOEs
280
280
230
220
270
210
190
Highspeed receiver/transmitter input and output clock period.
Highspeed receiver/transmitter input and output clock frequency.
De-serialization factor (width of parallel data bus).
provides high-speed timing specifications definitions.
Speed
High
IOEs
—
—
—
—
—
—
—
Column
Bottom
General Purpose
—
—
—
—
—
—
—
IOEs
Right
Row
—
—
—
—
—
—
—
Definitions
CLK [0,
10]
2, 8,
—
—
—
—
—
—
—
(2)
HighSpeed I/O Specifications
Notes
12..15]
[4..7,
CLK
280
280
230
220
270
210
190
(1),
PLL_OUT
(4)
280
280
230
220
270
210
190
(Part 2 of 2)
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
4–35