HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 180

• Manufacturer Part Number: HC230
• Description: HardCopy II Device Family
• Manufacturer: ALTERA [Altera Corporation]

HardCopy Series Handbook, Volume 1
7–16
Figure 7–7. Clock Attributes
The clock settings for PLL clocks are derived automatically based on the
PLL settings and reference clock characteristics. You can also override the
default PLL clock settings for timing analysis by specifying clock settings
for the input clock port on the PLL.
Clock uncertainty in PLL clock outputs is not modeled by default. You
should use the set_clock_uncertainty command to model jitter and
any other uncertainty and margin in your PLL clocks.
1
The SDC format provides a simple and easy method to constrain the
simplest to the most complex designs. The following example illustrates
the simplest SDC commands for a clock (port or pin) and for a generated
clock at the PLL output pin for a design:
#Constrain the base clock
create_clock -period 10.000 [get_ports clkin]
#Constrain the PLL output clock
derive_pll_clocks
1
Consult with your Altera Field Applications Engineer (FAE) or
use MySupport regarding PLL clock uncertainty calculation for
your design.
Although derive_pll_clocks is in the sdc_ext package, it is
the unique exception to the requirement that all timing
constraints in the HardCopy II design flow must be in the sdc
package. This command is automatically translated to the
sdc-package command generated_pll_clock prior to
transfer to the HCDC.
clk
Uncertainty
Clock
- 0.5
Rising Edge
of Clock
0.0
0.5
Clock Period = 10.0 ns
Falling Edge
of Clock
5.0
10.0
Altera Corporation
September 2008