HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 136

• Manufacturer Part Number: HC230
• Description: HardCopy II Device Family
• Manufacturer: ALTERA [Altera Corporation]

HardCopy Series Handbook, Volume 1
Creating a New
Project
6–8
f
The design flow of
design and migrates this design to a HardCopy II device target, or begins
with a HardCopy II target and migrates this design to a Stratix II target
for FPGA prototyping. The design flow for both cases is shown in
Figure
For more information on the HardCopy II design flow and alternative
methods to complete HardCopy II designs using the Quartus II GUI,
refer to the Quartus II Support for HardCopy II Devices chapter in the
Quartus II Handbook or the HardCopy II Design Considerations chapter in
volume 1 of the HardCopy Series Handbook.
The following sections describe each step of the flow shown in
and explains how each step is completed using the interactive Tcl shell.
Both FPGA and HardCopy design in the Quartus II software revolve
around the use of projects. You must create a project before you begin
working with a new design. A project includes source design files (RTL
and schematics), Quartus II tool settings, and a set of pin locations and
timing constraints. Although a project can contain many different
revisions for a design, each revision can have a unique set of design
constraints, target device settings, and Quartus II software settings. You
must explicitly open a project before you can perform other operations on
the project. You must close the current project to switch to a different
project or revision.
This section details the different operations relating to project
management using Tcl commands.
Creating a Stratix II Prototype Project
To create a new Stratix II prototype project, use the project_new Tcl
command. The syntax for this command is:
tcl> project_new [-family <family>] [-overwrite] \
The only required argument for this command is the project name,
<project name>, although the target device family, part code, and revision
name can be specified at this time also. By default, the revision name is
the same as the project name. The device family and part code can be set
later using the set_global_assignment command. For example, to create
[-part <part>] [-revision <revision_name>] \
<project_name>
6–1.
Figure 6–1
begins with a Stratix II FPGA prototype
Altera Corporation
September 2008
Figure 6–1