HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 17

• Manufacturer Part Number: HC230
• Description: HardCopy II Device Family
• Manufacturer: ALTERA [Altera Corporation]

PLLs and Clock
Networks
Altera Corporation
September 2008
f
outputs are cleared on power up. The designer needs to take these into
consideration when designing logic that might evaluate the initial
power-up values of the memory block.
HardCopy II embedded memory consists of M4K and M-RAM memory
blocks and have a one-to-one mapping from Stratix II M4K and M-RAM
resources.
blocks.
For more information on the Stratix II memory block features, refer to
the Stratix II Device Handbook.
Both HardCopy II enhanced and fast PLLs are feature rich, supporting
advanced capabilities such as clock switchover, reconfigurable phase
shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs are used
for general-purpose clock management, supporting multiplication,
division, phase shifting, and programmable duty cycle. In addition,
enhanced PLLs support external clock feedback mode, spread-spectrum
clocking, and counter cascading. Fast PLLs offer high speed outputs to
manage the high-speed differential I/O interfaces.
1
Similar to Stratix II FPGAs, HardCopy II devices also support a
power-down mode where unused clock networks can be disabled.
HardCopy II and Stratix II clock control blocks support dynamic
selection of the input clock from up to four possible sources, giving the
designer the flexibility to choose from multiple (up to four) clock sources.
All Stratix II PLL features are supported by HardCopy II PLLs.
Table 2–4
shows the size and features of the different RAM
PLLs and Clock Networks
Preliminary
2–9