ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet - Page 91

• Manufacturer Part Number: ZL50050GAC
• Description: 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Non-Multiplexed Microprocessor Port Timing
Note: High Impedance is measured by pulling to the appropriate rail with R
Note: There must be a minimum of 30 ns between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a
10
12
11
1
2
3
4
5
6
7
8
9
A0-A14
D0-D15
D0-D15
WRITE
READ
minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next access).
DTA
R/W
CS setup from DS falling
R/W setup from DS falling
Address setup from DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Data setup from DTA Low on Read
Data hold on read
Data setup on write
Data hold on write
Acknowledgment Delay:
Acknowledgment Hold Time
DS
CS
Reading/Writing Registers
Reading/Writing Memory
Characteristics
Figure 32 - Motorola Non-Multiplexed Bus Timing
t
t
ADS
CSS
t
Zarlink Semiconductor Inc.
RWS
Sym.
t
t
t
t
t
t
t
t
t
t
t
t
RWH
WDS
WDH
RWS
CSS
ADS
CSH
ADH
RDS
RDH
AKD
AKH
ZL50050
t
WDS
91
Min.
12
0
9
9
0
9
9
5
9
9
VALID ADDRESS
L
, with timing corrected to cancel time taken to discharge C
t
AKD
t
RDS
VALID WRITE DATA
Typ.
VALID READ DATA
Max.
4.5
88
80
11
t
t
CSH
WDH
t
RDH
t
t
Units
RWH
ADH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AKH
Memory Read
Register Read
C
C
Note 1
C
C
C
Note 1
Test Conditions
L
L
L
L
L
=60pF
=60pF, R
=60pF
=60pF
=60pF, R
V
V
V
V
V
Data Sheet
V
V
TT
TT
TT
TT
TT
TT
TT
L
L
=1k
=1k,
L
.