ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet - Page 35

• Manufacturer Part Number: ZL50050GAC
• Description: 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.2
Note that when the devices are operating in Local or Backplane 32 Mbps mode, some of the output streams (the
upper half of the available streams) are unused. The LE/BE bits of the channels on those output streams will
always be low. Therefore, the upper LSTo/BSTo pins are either driven HIGH or high impedance, in accordance with
the value of the LORS/BORS input signals, as shown in Table 2 on page 30.
The data (channel control bit) transmitted by L/BCSTo0-1 replicates the Local/Backplane Output Enable (LE/BE)
bit of the Local/Backplane Connection Memory, with a LOW state indicating the channel to be set to high
impedance. Refer to “Local Connection Memory Bit Definition,” on page 49 and “Backplane Connection Memory Bit
Definition,” on page 50 for more details.
The L/BCSTo0-1 pins transmit serial data (channel control bits) at 16.384 Mbps, with each bit representing the
per-channel high impedance state for a specific stream. Four output streams are allocated to each control line as
follows:
•
•
The channel control bit location, within a frame period, for each channel of the Local/Backplane output streams is
presented in Table 4, L/BCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode)
The L/BCSTo0-1 pins output data at a constant data rate of 16.384 Mbps and all output streams, L/BSTo0-7,
operate at a data rate of 32.768 Mbps.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 4:
1. The channel control bit corresponding to Stream 0, Channel 0, L/BSTo0_Ch0, is transmitted on L/BCSTo0 and
2. The channel control bit corresponding to Stream 6, Channel 0, L/BSTo6_Ch0, is transmitted on L/BCSTo0 in
3. For stream L/BSTo2, the value of the channel control bit for Channel 511 will be transmitted during the C16o
4. For stream L/BSTo3, the value of the channel control bit for Channel 5 will be transmitted during the C16o clock
L/BCSTo0 outputs the channel control bits for streams L/BSTo0, 2, 4, and 6
L/BCSTo1 outputs the channel control bits for streams L/BSTo1, 3, 5, and 7
is advanced, relative to the frame boundary, by ten periods (clock period number 2039) of C16o.
advance of the frame boundary by seven periods (clock period number 2042) of output clock, C16o. Similarly,
the channel control bits for L/BSTo7_Ch0 are advanced relative to the frame boundary by seven periods of
C16o on L/BCSTo1.
clock period number 2036 on L/BCSTo0.
period number 12 on L/BCSTo1.
LORS/BORS Asserted LOW, 32 Mbps Mode
Zarlink Semiconductor Inc.
ZL50050
35
Data Sheet