ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet - Page 10

• Manufacturer Part Number: ZL50050GAC
• Description: 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description
Device Timing
Pin Name
FP16o
FP8o
C16o
FP8i
C8o
C8i
Coordinates
Package
(196-ball
ZL50050
PBGA)
M10
P10
N10
N11
P12
M9
Master Clock (5 V Tolerant Schmitt-Triggered Input). This pin accepts an
8.192 MHz clock. The internal frame boundary is aligned with the clock falling
or rising edge, as controlled by the C8IPOL bit in the Control Register. Input
data on both the Backplane and Local sides (BSTi0-15 and LSTi0-15) must be
aligned to this clock and the accompanying input frame pulse, FP8i.
Frame Pulse Input (5 V Tolerant Schmitt-Triggered Input). When the
Frame Pulse Width bit (FPW) of the Control Register is LOW (default), this pin
accepts a 122 ns-wide frame pulse. When the FPW bit is HIGH, this pin
accepts a 244 ns-wide frame pulse. The device will automatically detect
whether an ST-BUS or GCI-Bus style frame pulse is applied. Input data on
both the Backplane and Local sides (BSTi0-15 and LSTi0-15) must be aligned
to this frame pulse and the accompanying input clock, C8i.
C8o Output Clock (5 V Tolerant Three-state Output). This pin outputs an
8.192 MHz clock generated within the device. The clock falling edge or rising
edge is aligned with the output frame boundary presented on FP8o; this edge
polarity alignment is controlled by the COPOL bit of the Control Register.
Output data on both the Backplane and Local sides (BSTo0-15 and LSTo0-15)
will be aligned to this clock and the accompanying output frame pulse, FP8o.
Frame Pulse Output (5 V Tolerant Three-state Output). When the Frame
Pulse Width bit (FPW) of the Control Register is LOW (default), this pin
outputs a 122ns-wide frame pulse. When the FPW bit is HIGH, this pin outputs
a 244 ns-wide frame pulse. The frame pulse, running at 8 kHz rate, will have
the same format (ST-BUS or GCI-Bus) as the input frame pulse (FP8i). Output
data on both the Backplane and Local sides (BSTo0-15 and LSTo0-15) will be
aligned to this frame pulse and the accompanying output clock, C8o.
C16o Output Clock (5 V Tolerant Three-state Output). This pin outputs a
16.384 MHz clock generated within the device. The clock falling edge or rising
edge is aligned with the output frame boundary presented on FP16o; this edge
polarity alignment is controlled by the COPOL bit of the Control Register.
Output data on both the Backplane and Local sides (BSTo0-15 and LSTo0-15)
will be aligned to this clock and the accompanying output frame pulse, FP16o.
Frame Pulse Output (5 V Tolerant Three-state Output). When the Frame
Pulse Width bit (FPW) of the Control Register is LOW (default), this pin
outputs a 61 ns-wide frame pulse. When the FPW bit is HIGH, this pin outputs
a 122 ns-wide frame pulse. The frame pulse, running at 8 kHz rate, will have
the same format (ST-BUS or GCI-Bus) as the input frame pulse (FP8i). Output
data on both the Backplane and Local sides (BSTo0-15 and LSTo0-15) will be
aligned to this frame pulse and the accompanying output clock, C16o.
Zarlink Semiconductor Inc.
ZL50050
10
Description
Data Sheet