ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet - Page 23
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ZL50050GAC
Manufacturer Part Number
ZL50050GAC
Description
8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50050GAC.pdf
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ZL50050
Data Sheet
2.2
Frame Pulse Input and Master Input Clock Timing
The input frame pulse (FP8i) is an 8 kHz input signal active for 122 ns or 244 ns at the frame boundary. The FPW
bit in the Control Register must be set according to the applied pulse width. See Pin Description and Table 19,
“Control Register Bits” on page 53, for details.
The active state and timing of FP8i can conform either to the ST-BUS or to the GCI-Bus as shown in Figure 6,
ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates. The ZL50050 device will automatically detect
whether an ST-BUS or a GCI-Bus style frame pulse is being used for the master frame pulse (FP8i). The output
frame pulses (FP8o and FP16o) are always of the same style (ST-BUS or GCI-Bus) as the input frame pulse. The
active edge of the input clock (C8i) shall be selected by the state of the Control Register bit C8IPOL.
Note that the active edge of ST-BUS is falling edge, which is the default mode of the device, while GCI-Bus uses
rising edge as the active edge. Although GCI frame pulse will be automatically detected, to fully conform to
GCI-Bus operation, the device should be set to use C8i rising edge as the active edge (by setting bit C8IPOL HIGH)
when GCI-Bus is used.
For the purposes of describing the device operation, the remaining part of this document assumes the ST-BUS
frame pulse format with a single width frame pulse of 122 ns and a falling active clock-edge, unless explicitly stated
otherwise.
In addition, the device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to
the output ports. The generated frame pulses (FP8o, FP16o) will be provided in the same format as the master
frame pulse (FP8i). The polarity of C8o and C16o, at the frame boundary, can be controlled by the Control Register
bit, COPOL. An analog phase lock loop (APLL) is used to multiply the input clock frequency on C8i to generate an
internal clock signal operating at 131.072 MHz.
23
Zarlink Semiconductor Inc.
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