ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet - Page 66

• Manufacturer Part Number: ZL50050GAC
• Description: 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

14.8
Addresses 0083
Sixteen Local Output Advancement Registers (LOAR0 to LOAR15) allow users to program the output advancement
for output data streams LSTo0 to LSTo15.
For 2 Mbps, 4 Mbps, 8 Mbps and 16 Mbps stream operation, the possible adjustment is -2 (15 ns), -4 (31 ns) or -6
(46 ns) cycles of the internal system clock (131.072 MHz).
For 32 Mbps stream operation, the possible adjustment is -1 (7.6 ns), -2 (15 ns) or -3 (23 ns) cycles of the internal
system clock (131.072 MHz).
The LOAR0 to LOAR15 registers are configured as follows:
14.8.1
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
Non-32 Mbps Mode, n = 0 to 7
(where n = 0 to 15 for Local
for Local 32 Mbps Mode)
2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps
Local Output Advancement For
Local Output Advancement Registers (LOAR0 to LOAR15)
Table 29 - Backplane Input Bit Delay and Sampling Point Programming Table (continued)
Local Output Advancement Bits 1-0 (LOA1-LOA0)
LOARn Bit
BID4
Clock Rate 131.072 MHz
1
1
1
1
1
15:2
1:0
-2 cycles (~15 ns)
H
to 0092
0 (Default)
BID3
Table 31 - Local Output Advancement (LOAR) Programming Table
1
1
1
1
1
Table 30 - Local Output Advancement Register (LOAR) Bits
H
.
BIDn
BID2
0
1
1
1
1
Reserved
LOA[1:0]
Name
BID1
1
0
0
1
1
Zarlink Semiconductor Inc.
BID0
ZL50050
Reset
1
0
1
0
1
Value
0
0
Advancement For 32 Mbps
66
Clock Rate 131.072 MHz
SMPL_MODE
Input Data
-1 cycle (~7.6 ns)
Bit Delay
Reserved
Must be set to 0 for normal operation
Local Output Advancement Value
= LOW
Local Output
6 3/4
7 1/4
7 1/2
7 3/4
0 (Default)
7
Input Data
Bit Delay
Description
6
7
7
7
7
SMPL_MODE
= HIGH
Advancement Bits
Input Data
LOA1
Sampling
Corresponding
0
0
Point
2/4
3/4
4/4
1/4
2/4
Data Sheet
LOA0
0
1