ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet - Page 72

• Manufacturer Part Number: ZL50050GAC
• Description: 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

14.11.3
Address 00CA
Backplane Receive BER Length Register (BRXBLR) defines how many channels of the BER sequence will be
received in each frame.
The BRXBLR register is configured as follows:
14.11.4
Address 00CB
Backplane BER Start Receive Register defines the input stream and the start channel at which the BER sequence
shall start to be received. The BBSRR register is configured as follows:
15:14
13:9
15:9
Bit
8:0
Bit
8:0
BBRCA[8:0]
BBRSA[4:0]
BRXBL[8:0]
Backplane Receive BER Length Register (BRXBLR)
Backplane BER Start Receive Register (BBSRR)
Reserved
Reserved
Name
Name
H
H
.
.
Table 44 - Backplane BER Start Receive Register (BBSRR) Bits
Table 43 - Backplane Receive BER Length (BRXBLR) Bits
Reset
Value
Reset
Value
0
0
0
0
0
Reserved
Must be set to 0 for normal operation
Backplane Receive BER Length Bits
The binary value of these bits defines the number of channels in addition to
the Start Channel allocated for the BER Receiver. (i.e., Total Channels =
BRXBL value + 1)
Reserved
Must be set to 0 for normal operation
Backplane BER Receive Stream Address Bits
The binary value of these bits refers to the Backplane input stream configured
to receive the BER data.
Backplane BER Receive Channel Address Bits
The binary value of these bits refers to the Backplane input channel at which
the BER data starts to be compared.
Zarlink Semiconductor Inc.
ZL50050
72
Description
Description
Data Sheet