ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet - Page 44
![no-image](/images/no-image-200.jpg)
ZL50020GAC
Manufacturer Part Number
ZL50020GAC
Description
Enhanced 2 K Digital Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50020GAC.pdf
(83 pages)
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15 - 9
External Read/Write Address: 0003
Reset Value: 0000
15
Bit
0
8
7
6
5
4
3
2
1
0
14
0
CKOFPO3
CKOFPO2
CKOFPO1
CKOFPO0
FPOF2EN
FPOF1EN
FPOF0EN
Unused
Unused
Unused
Name
13
EN
EN
EN
EN
0
Table 16 - Output Clock and Frame Pulse Control Register (OCFCR) Bits
H
12
0
Reserved
In normal functional mode, these bits MUST be set to zero.
FPo_OFF2 Enable
When this bit is high, output frame pulse FPo_OFF2
When this bit is low, output frame pulse FPo_OFF2.
FPo_OFF1 Enable
When this bit is high, output frame pulse FPo_OFF1 is enabled.
When this bit is low, output frame pulse FPo_OFF1 is in high impedance state.
FPo_OFF0 Enable
When this bit is high, output frame pulse FPo_OFF0 is enabled.
When this bit is low, output frame pulse FPo_OFF0 is in high impedance state.
Reserved
In normal functional mode, these bits MUST be set to zero.
Reserved
In normal functional mode, these bits MUST be set to zero.
CKo3 and FPo3 Enable
When this bit is high, output clock CKo3 and output frame pulse FPo3 are enabled.
When this bit is low, CKo3 and FPo3 are in high impedance state.
CKo2 and FPo2 Enable
When this bit is high, output clock CKo2 and output frame pulse FPo2 are enabled.
When this bit is low, CKo2 and FPo2 are in high impedance state.
CKo1 and FPo1 Enable
When this bit is high, output clock CKo1 and output frame pulse FPo1 are enabled.
When this bit is low, CKo1 and FPo1 are in high impedance state.
CKo0 and FPo0 Enable
When this bit is high, output clock CKo0 and output frame pulse FPo0 are enabled.
When this bit is low, CKo0 and FPo0 are in high impedance state.
11
0
H
10
0
9
0
Zarlink Semiconductor Inc.
FPOF2
EN
8
ZL50020
FPOF1
44
EN
7
FPOF0
Description
EN
6
5
0
4
0
FPO3
CKO
EN
3
FPO2
CKO
EN
2
FPO1
CKO
Data Sheet
EN
1
FPO0
CKO
EN
0
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