ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet - Page 20
ZL50020GAC
Manufacturer Part Number
ZL50020GAC
Description
Enhanced 2 K Digital Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50020GAC.pdf
(83 pages)
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The output timing is dependent on the operation mode that is selected. When the device is in Divided Clock mode,
the frequencies on CKo0 - 3 cannot be greater than the input clock, CKi. For example, if the input clock is
8.192 MHz, the CKo2 pin will not produce a valid output clock and the CKo3 pin can only be programmed to output
a 4.096 MHz or 8.192 MHz clock signal.
The device also delivers positive or negative output frame pulse and ST-BUS/GCI-Bus output clock formats via the
programming of various bits in the Output Clock and Frame Pulse Selection Register (OCFSR). By default, the
device delivers the negative output clock format. The ZL50020 can also deliver GCI-Bus format output frame pulses
by programming bits of the Output Clock and Frame Pulse Selection Register (OCFSR). As there is a separate bit
setting for each frame pulse output, some of the outputs can be set to operate in ST-BUS mode and others in
GCI-Bus mode.
The following figures describe the usage of the FPO0P, FPO1P, FPO2P, FPO3P, CKO0P, CKO1P, CKO2P and
CKO3P bits to generate the FPo0 - 3 and CKo0 - 3 timing.
CKOFPO0EN = 1
FPO0P = 0
FPO0POS = 0
CKOFPO0EN = 1
FPO0P = 1
FPO0POS = 0
CKOFPO0EN = 1
FPO0P = 0
FPO0POS = 1
CKOFPO0EN = 1
FPO0P = 1
FPO0POS = 1
CKOFPO0EN = 1
CKO0P = 0
CKo0 = 4.096 MHz
CKOFPO0EN = 1
CKO0P = 1
CKo0 = 4.096 MHz
FPo0 pulse width
CKo0
FPo1 pulse width
CKo1
FPo2 pulse width
CKo2
FPo3 pulse width
CKo3
Figure 7 - Output Timing for CKo0 and FPo0
Table 3 - Output Timing Generation
4.096, 8.192, 16.384 or 32.768
Zarlink Semiconductor Inc.
244, 122, 61 or 30
ZL50020
16.384
4.096
8.192
244
122
61
20
MHz
MHz
MHz
MHz
ns
ns
ns
ns
Data Sheet
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