ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet - Page 35
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ZL50020GAC
Manufacturer Part Number
ZL50020GAC
Description
Enhanced 2 K Digital Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50020GAC.pdf
(83 pages)
15.0
The ZL50020 provides per-channel code translation to be used to adapt pulse code modulation (PCM) voice or
data traffic between networks which use different encoding laws. Code translation is valid in both Connection Mode
and Message Mode.
In order to use this feature, the Connection Memory High (CM_H) entry for the output channel must be
programmed. V/D (bit 4) defines if the traffic in the channel is voice or data. Setting ICL1 - 0 (bits 3 - 2) programs the
input coding law and OCL1 - 0 (bits 1- 0) programs the output coding law as shown in Table 9.
The different code options are:
For voice coding options, the ITU-T G.711 A-law and ITU-T G.711 µ-law are the standard rules for encoding. A-law
without Alternate Bit Inversion (ABI) is an alternative code that does not invert the even bits (6, 4, 2, 0). µ-law
without Magnitude Inversion (MI) is an alternative code that does not perform inversion of magnitude bits (6, 5, 4, 3,
2, 1, 0).
When transferring data code, the option “no code” does not invert the bits. The Alternate Bit Inversion (ABI) option
inverts the even bits (6, 4, 2, 0) while the Inverted Alternate Bit Inversion (ABI) inverts the odd bits (7, 5, 3, 1). When
the “All bits inverted” option is selected, all of the bits (7, 6, 5, 4, 3, 2, 1, 0) are inverted.
The input channel and output channel encoding law are configured independently. If the output channel coding is
set to be different from the input channel, the ZL50020 performs translation between the two standards. If the input
and output encoding laws are set to the same standard, no translation occurs. As the V/D (bit 4) of the Connection
Memory High (CM_H) must be set on a per-channel basis, it is not possible to translate between voice and data
encoding laws.
16.0
By programming the Stream Input Quadrant Frame Registers (SIQFR0 - 31), users can divide one frame of input
data into four quadrant frames and can force the LSB or MSB of every input channel in these quadrants to one or
zero for robbed-bit signaling. The four quadrant frames are defined as follows:
Input Coding
(ICL1- 0)
16.384 Mbps
PCM A-law/µ-law Translation
Quadrant Frame Programming
2.048 Mbps
4.096 Mbps
8.192 Mbps
Data Rate
00
01
10
11
Channel 0 - 15
Channel 0 - 31
Channel 0 - 63
Channel 0 - 7
Table 10 - Definition of the Four Quadrant Frames
Output Coding
Quadrant 0
Table 9 - Input and Output Voice and Data Coding
(OCL1 - 0)
00
01
10
11
Zarlink Semiconductor Inc.
Channel 64 - 127
Channel 16 - 31
Channel 32 - 63
Channel 8 - 15
ZL50020
Quadrant 1
ITU-T G.711 A-law
ITU-T G.711 µ-law
A-law without Alternate Bit
Inversion (ABI)
µ-law without Magnitude
Inversion (MI)
35
Voice Coding
(V/D bit = 0)
Channel 128 - 191
Channel 16 - 23
Channel 32 - 47
Channel 64 - 95
Quadrant 2
No code
Alternate Bit Inversion (ABI)
Inverted Alternate Bit
Inversion (ABI)
All bits inverted
Channel 192 - 255
Channel 96 - 127
Channel 24 - 31
Channel 48 - 63
Data Coding
(V/D bit = 1)
Quadrant 3
Data Sheet