ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet - Page 42

• Manufacturer Part Number: ZL50020GAC
• Description: Enhanced 2 K Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

External Read/Write Address: 0001
Reset Value: 0000
3 - 1
Bit
0
15
0
14
0
BPD2 - 0
MBPS
Name
H
13
0
Table 14 - Internal Mode Selection Register (IMS) Bits (continued)
12
0
Block Programming Data
These bits refer to the value to be loaded into the connection memory, whenever the
memory block programming feature is activated. After the MBPE bit in the Control
Register is set to high and the MBPS bit in this register is set to high, the contents of
the bits BPD2 - 0 are loaded into bits 2 - 0 of the Connection Memory Low. Bits 15 - 3
of the Connection Memory Low and bits 15 - 0 of Connection Memory High are
zeroed.
Memory Block Programming Start:
A zero to one transition of this bit starts the memory block programming function. The
MBPS and BPD2 - 0 bits in this register must be defined in the same write operation.
Once the MBPE bit in the Control Register is set to high, the device requires two
frames to complete the block programming. After the programming function has fin-
ished, the MBPS bit returns to low, indicating the operation is completed. When MBPS
is high, MBPS or MBPE can be set to low to abort the programming operation.
Whenever the microprocessor writes a one to the MBPS bit, the block programming
function is started. As long as this bit is high, the user must maintain the same logical
value to the other bits in this register to avoid any change in the device setting.
11
0
H
10
0
9
0
Zarlink Semiconductor Inc.
PD_EN
STIO_
8
ZL50020
42
BDH
7
Description
BDL
6
RBER
EN
5
TBER
EN
4
BPD
3
2
BPD
2
1
BPD
1
0
Data Sheet
MBPS
0