ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet - Page 18

• Manufacturer Part Number: ZL50020GAC
• Description: Enhanced 2 K Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The ZL50020 accepts positive and negative ST-BUS/GCI-Bus input clock and input frame pulse formats via the
programming of CKINP (bit 8) and FPINP (bit 7) in the Control Register (CR). By default, the device accepts the
negative input clock format and ST-BUS format frame pulses. However, the switch can also accept a positive-going
clock format by programming CKINP (bit 8) in the Control Register (CR). A GCI-Bus format frame pulse can be
used by programming FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR).
FPi (244 ns)
FPINP = 0
FPINPOS = 0
FPi (244 ns)
FPINP = 1
FPINPOS = 0
FPi (244 ns)
FPINP = 0
FPINPOS = 1
FPi (244 ns)
FPINP = 1
FPINPOS = 1
CKi
(4.096 MHz)
CKINP = 0
CKi
(4.096 MHz)
CKINP = 1
STi
(2.048 Mbps)
FPi (122 ns)
FPINP = 0
FPINPOS = 0
FPi (122 ns)
FPINP = 1
FPINPOS = 0
FPi (122 ns)
FPINP = 0
FPINPOS = 1
FPi (122 ns)
FPINP = 1
FPINPOS = 1
CKi
(8.192 MHz)
CKINP = 0
CKi
(8.192 MHz)
CKINP = 1
STi
(4.096 Mbps)
1
Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the CR
Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the CR
0
0
7
Channel 0
7
Channel 0
6
Zarlink Semiconductor Inc.
5
ZL50020
6
4
18
1
2
Channel 31
Channel 63
1
0
0
7
7
Data Sheet
6