ZL50020GAC ZARLINK [Zarlink Semiconductor Inc], ZL50020GAC Datasheet - Page 13
![no-image](/images/no-image-200.jpg)
ZL50020GAC
Manufacturer Part Number
ZL50020GAC
Description
Enhanced 2 K Digital Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50020GAC.pdf
(83 pages)
- Current page: 13 of 83
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B6, C6, D5,
C5, C4, E3,
C2, B2, D2,
D4, B4, B3,
F2, E1, D1,
A7, A5, A6,
A4, A3, A2,
F3, F4, E2,
G1, F1, J1,
H1, K1, L1,
PBGA Pin
Number
C1, B1
B10
B11
LQFP Pin
179, 180,
181, 182,
183, 184,
185, 187,
198, 200,
201, 202,
203, 204,
205, 206,
243, 244,
245, 246,
247, 248,
250, 252,
189, 190,
191, 192,
193, 194,
196, 197
Number
155
154
Pin Name
STi0 - 31
CKi
FPi
Zarlink Semiconductor Inc.
ST-BUS/GCI-Bus
Schmitt-Triggered Input)
This pin accepts the frame pulse which stays active for 61 ns,
122 ns or 244 ns at the frame boundary. The frame pulse
frequency is 8 kHz. The frame pulse associated with the CKi must
be applied to this pin. If the data rate is 16.384 Mbps, a 61 ns wide
frame pulse must be used. By default, the device accepts a
negative frame pulse in ST-BUS format, but it can accept a
positive frame pulse instead if the FPINP bit is set high in the
Control Register (CR). It can accept a GCI-formatted frame pulse
by programming the FPINPOS bit in the Control Register (CR) to
high.
ST-BUS/GCI-Bus Clock Input (5 V-Tolerant Schmitt-Triggered
Input)
This pin accepts a 4.096 MHz, 8.192 MHz or 16.384 MHz clock.
In divided clock mode the clock frequency applied to this pin must
be twice the highest input or output data rate. In multiplied clock
mode the clock frequency applied to this pin must be twice the
highest input data rate.
The exception is, when data is running at 16.384 Mbps, a
16.384 MHz clock must be used. By default, the clock falling edge
defines the input frame boundary, but the device allows the clock
rising edge to define the frame boundary by programming the
CKINP bit in the Control Register (CR).
Serial Input Streams 0 to 31 (5 V-Tolerant Inputs with Internal
Pull-downs)
The data rate of each input stream can be selected independently
using the Stream Input Control Registers (SICR[n]). In the
2.048 Mbps mode, these pins accept serial TDM data streams at
2.048 Mbps with 32 channels per frame. In the 4.096 Mbps mode,
these pins accept serial TDM data streams at 4.096 Mbps with 64
channels per frame. In the 8.192 Mbps mode, these pins accept
serial TDM data streams at 8.192 Mbps with 128 channels per
frame. In the 16.384 Mbps mode, these pins accept TDM data
streams at 16.384 Mbps with 256 channels per frame.
ZL50020
13
Frame
Description
Pulse
Input
(5 V-Tolerant
Data Sheet
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