MT90222 ZARLINK [Zarlink Semiconductor Inc], MT90222 Datasheet - Page 79
MT90222
Manufacturer Part Number
MT90222
Description
4/8/16 Port IMA/TC PHY Device
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.MT90222.pdf
(155 pages)
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Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Bin):
15:12
Bit #
7:0
10
15
14
13
12
10
11
11
...
9
8
9
8
7
6
1
0
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
...
R
R
Unused. Read all 0’s.
Reserved. Write 0 for normal operation
Reserved. Write 0 for normal operation
Write 0 for normal operation, 1 to tristate parity.
Parity Bit. EVEN parity is selected when this bit is set. ODD parity is selected when this bit
is cleared.
User Defined Byte. This byte is inserted into the sixth byte of the header when cells are
being output in 16-bit mode.
Reserved.
Reserved. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
16/8-bit mode selection bit for the RX UTOPIA data bus. When set the RX UTOPIA
interface is operating in 8-bit mode, when reset it is operating in 16-bit mode.
Reserved. Write 0 for normal operation.
Reset UTOPIA RX state machines when set to 1.
Reserved. Write 0 for normal operation.
Enable UTOPIA PHY address of IMA Group 7. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 6. A 1 enables the PHY port Address.
...
Enable UTOPIA PHY address of IMA Group 1. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 0. A 1 enables the PHY port Address.
0x0012 (1 reg)
1 register which contains the User Defined Byte. This byte is inserted into the
sixth byte of the header when operating in sixteen-bit mode.
0000
0x0011 (1 reg)
1 register to enable the IMA Groups. For MT90222 only groups 0, 1, 2 and 3 are
used.
X000000000000000
Table 10 - UTOPIA Output Group PHY Enable Register
Table 11 - UTOPIA Output User Defined Byte
Zarlink Semiconductor Inc.
MT90222/3/4
79
Description
Description
Data Sheet
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