MT90222 ZARLINK [Zarlink Semiconductor Inc], MT90222 Datasheet - Page 53

• Manufacturer Part Number: MT90222
• Description: 4/8/16 Port IMA/TC PHY Device
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.1
In this mode, all links are active and can be used. Its minor modes of operation include Generic 1.544 MHz mode
(F-bit and 24 time slots), Generic 2.048 MHz mode (32 time slots), and ST-BUS mode (32 time slots).
Mapping registers are used to determine when a time slot is used to carry the ATM traffic. There are two 16-bit
mapping registers for each TDM TX and for each TDM RX links. Each bit of the 2 registers (total of 32 bits) controls
one time slot. A bit value of 1 corresponds to an active time slot. A value of 0 corresponds to an inactive time slot
and the output is in High Impedance mode for that time slot. The TDM TX link is independent of the TDM RX link
and can have different mapping (using different time slots and optionally a different number of time slots).
Fractional T1/E1 and nx64 channel modes are implemented by programming bits in the mapping registers to enable
the use of the required time slots.
4.1.1
This is also known as T1 generic mode. In this mode, data rate is 1.544 Mb/s, clock is 1.544 MHz and frame pulse
is 8 KHz. A frame is 193 bits long and a frame pulse is present (either generated or accepted as input). The first bit,
indicated by the frame pulse, is not used to carry any useful information; it is in high impedance on Tx link and is
ignored on Rx link. The 24 time slots (192 bits) are controlled by the lowest 24 bits of the mapping register associated
with a link. Fractional T1 is supported by activating (selecting) any of the first 24 time slots defined in the mapping
register.
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
the following settings.
4.1.2
This is used for generic nx64 connections, where n can be any number from 1 to 32. In this mode, data rate is
2.048 Mb/s. A clock of 2.048 MHz is used and the Frame pulse is indicating the first bit of the first time slot of a frame
of 32 time slots. The mapping registers are used to determine the number of time slots used and their position in the
frame. This enables a direct interface to existing T1 or E1 framers and opens up the option to interface to generic
nx64 devices. Fractional T1/E1 is supported as well by selecting the time slots that are used to carry ATM traffic.
Note: Both frame pulse polarity and clock edge are programmable.
Single Mode
Data rate (bits 6:5) = 00
Multiplex mode (bits 4:3) = 00
Clock and Sync format (bit 2) = 0
Cell delineation mode (bit 10 of TDM RX Link Control only) = 0
Single Mode - Generic 1.544 MHz
Single mode - Generic 2.048 MHz
T1 Frame
Bit Cells
at DSTx0-15
Serial Bit
Stream
TXSYNC
TXCK
RXSYNC
RXCK
Figure 11 - Single Mode - Generic 1.544 MHz
Bit Cell
bit 193
Zarlink Semiconductor Inc.
MT90222/3/4
High Impedance
53
Unused or
bit 1
Bit Cell
bit 2
...
...
...
...
...
Data Sheet