MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 92

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

Specifications
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and
setup time, according to:
In most of case, duty cycle is 50 / 50, therefore:
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
Falling-edge latch data
92
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
Ref No.
5
6
Table 43. Non-Gated Clock Mode Parameters (Continued)
csi_pixclk low time
csi_pixclk frequency
MC9328MX1 Advance Information, Rev. 4
Parameter
Minimum
10.42
0
Maximum
48
–
Unit
MHz
ns
Freescale Semiconductor