MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 26

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

Specifications
26
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only
when EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Number
10
11
1
2
3
4
5
6
7
8
9
Table 15. Parameters for Read Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
OE and EB assertion time
CS pulse width
OE negated before CS5 is negated
Address inactive before CS negated
Data hold timing after OE negated
Data ready after DTACK is asserted
CS deactive to next CS active
OE negate after EB negate
DTACK pulse width
DTACK asserted after CS5 asserted
DTACK asserted to OE negated
Characteristic
MC9328MX1 Advance Information, Rev. 4
See note 2
0.5T+0.24
Minimum
3T+2.2
0.5
3T
1T
T
–
–
0
–
(3.0 ± 0.3) V
Maximum
0.5T+0.67
4T+6.86
1019T
0.93
1.5
Freescale Semiconductor
3T
T
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns