MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 71

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

3.16 Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS, MS_SDIO,
and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in either four-state or
two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according to its
attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet transmissions occur.
During the BS1, BS2, and BS3 states, packet communications are executed. The BS1, BS2, and BS3 states are
regarded as one packet length and one communication transfer is always completed within one packet length (in
four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When an error
occurs during packet communication, the mode is shifted to two-state access mode, and the BS0 and BS1 bus states
are automatically repeated to avoid a bus collision on the SDIO.
Freescale Semiconductor
DAT[2]
DAT[1]
For 4-bit
For 4-bit
CMD
S
S
Block Data
Block Data
******
E Z Z
E
Z Z L H
Figure 54. SDIO ReadWait Timing Diagram
L L L L L L L L L L L L L L L L L L L L L H Z S
MC9328MX1 Advance Information, Rev. 4
P S T
CMD52
CRC
E Z Z
Z
S
Block Data
Block Data
******
E
E
Specifications
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