MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 29

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

Freescale Semiconductor
Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz (Continued)
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4.The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Number
10
11
12
7
8
9
Data hold timing after RW negated
Data ready after CS5 is asserted
CS deactive to next CS active
EB negate to CS negate
DTACK pulse width
DTACK asserted to RW negated
Characteristic
MC9328MX1 Advance Information, Rev. 4
0.5T+0.74
Minimum
1.5T-0.59
2T+1.8
1T
–
T
(3.0 ± 0.3) V
Maximum
0.5T+2.17
3T+5.26
3T
–
T
–
Specifications
Unit
ns
ns
ns
ns
ns
ns
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