MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 70

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

Specifications
3.15.2 SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the interrupt
response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data in this mode. The
memory controller generates an interrupt according to this low and the system interrupt continues until the source
is removed (SD_DAT[1] returns to its high level).
In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the "Interrupt Period"
during the data access, and the controller must sample SD_DAT[1] during this short period to determine the IRQ
status of the attached card. The interrupt period only happens at the boundary of each block (512 bytes).
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In this
mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the clock
running, and allows the user to submit commands as normal. After all commands are submitted, the user can switch
back to the data transfer operation and all counter and status values are resumed as access continues.
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MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL)
Command response cycle
Identification response cycle
Access time delay cycle
Command read cycle
Command-command cycle
Command write cycle
Stop transmission cycle
TAAC: Data read access time -1 defined in CSD register bit[119:112]
NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register bit[111:104]
DAT[1]
DAT[1]
For 4-bit
For 1-bit
CMD
S T
Interrupt Period
Parameter
Content
Table 31. Timing Values for Figure 48 through Figure 52
CRC
E Z Z P
Figure 53. SDIO IRQ Timing Diagram
MC9328MX1 Advance Information, Rev. 4
S
S
Response
Symbol
NWR
NCR
NRC
NCC
NAC
NST
NID
Block Data
Interrupt Period
E Z Z
L H
E
Minimum
Z
2
5
2
8
8
2
2
IRQ
TAAC + NSAC
******
S
Maximum
Block Data
64
5
–
–
–
2
Freescale Semiconductor
E
Z
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Z Z
Unit
IRQ