MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 30
MC9328MX1/D
Manufacturer Part Number
MC9328MX1/D
Description
i.MX Integrated Portable System Processor
Manufacturer
ETC
Datasheet
1.MC9328MX1D.pdf
(96 pages)
- Current page: 30 of 96
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Specifications
3.9.3 EIM External Bus Timing
The following timing diagrams show the timing of accesses to memory or a peripheral.
30
BCLK (burst clock)
hsel_weim_cs[0]
EBx
EBx
weim_hready
weim_hrdata
1
1
(EBC
(EBC
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
hready
ADDR
htrans
hwrite
DATA
haddr
CS2
R/W
2
2
LBA
hclk
=0)
=1)
OE
Last Valid Address
Seq/Nonseq
Figure 10. WSC = 1, A.HALF/E.HALF
Read
MC9328MX1 Advance Information, Rev. 4
V1
Last Valid Data
Read
V1
V1
V1
Freescale Semiconductor
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