MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 18
![no-image](/images/no-image-200.jpg)
MC9328MX1/D
Manufacturer Part Number
MC9328MX1/D
Description
i.MX Integrated Portable System Processor
Manufacturer
ETC
Datasheet
1.MC9328MX1D.pdf
(96 pages)
- Current page: 18 of 96
- Download datasheet (2Mb)
Specifications
3.6 Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift
register comprised of the following:
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field,
and a 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field
is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing
diagram for the ETM9 is shown in Figure 2. See Table 10 on page 18 for the ETM9 timing parameters used in
Figure 2.
18
•
•
•
Ref No.
32-bit data field
7-bit address field
A read/write bit
2a
2b
3a
3b
4a
4b
1
CLK frequency
Clock high time
Clock low time
Clock rise time
Clock fall time
Output hold time
Output setup time
(Half-Rate Clocking Mode)
Parameter
Output Trace Port
Table 10. Trace Port Timing Diagram Parameter Table
TRACECLK
TRACECLK
Figure 2. Trace Port Timing Diagram
MC9328MX1 Advance Information, Rev. 4
3a
Minimum
2.28
3.42
1.3
0
3
–
–
1.8V +/- 0.10V
3b
2a
Maximum
4a
2b
85
–
–
4
3
–
–
Valid Data
Minimum
1
0
2
2
–
–
2
3
3.0V +/- 0.30V
Valid Data
Maximum
4b
Freescale Semiconductor
100
–
–
3
3
–
–
Unit
MHz
ns
ns
ns
ns
ns
ns
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