MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 61
MC9328MX1/D
Manufacturer Part Number
MC9328MX1/D
Description
i.MX Integrated Portable System Processor
Manufacturer
ETC
Datasheet
1.MC9328MX1D.pdf
(96 pages)
- Current page: 61 of 96
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Freescale Semiconductor
SCLK, MOSI, MISO
SCLK, MOSI, MISO
SCLK, MOSI, MISO
SS (output)
SS (input)
SS (input)
Figure 44. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge
Figure 42. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger
Figure 43. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
Ref
No.
1
2
3
4
5
6
7
Table 26. Timing Parameter Table for Figure 40 through Figure 44
1.
2.
3.
T = CSPI system clock period (PERCLK2).
Tsclk = Period of SCLK.
WAIT = Number of bit clocks (SCLK) or 32.768 KHz clocks per Sample
Period Control Register.
SPI_RDY to SS output low
SS output low to first SCLK edge
Last SCLK edge to SS output high
SS output high to SPI_RDY low
SS output pulse width
SS input low to first SCLK edge
SS input pulse width
6
MC9328MX1 Advance Information, Rev. 4
Parameter
7
Tsclk + WAIT
Minimum
3·Tsclk
2·Tsclk
2T
0
T
T
1
2
3
Maximum
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
Specifications
61
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