GS1503BCVE2 GENNUM [Gennum Corporation], GS1503BCVE2 Datasheet - Page 81

• Manufacturer Part Number: GS1503BCVE2
• Description: HD Embedded Audio CODEC Data Sheet
• Manufacturer: GENNUM [Gennum Corporation]

Table 5-29: Demultiplex Mode Host Interface Registers (Continued)
GS1503B HD Embedded Audio CODEC
Data Sheet
37953 - 1
Control
Item
Name
ASXB
DEL1-2B[25:0]
DEL3-4B[25:0]
RSRVB[17:0]
RSV
CTRONA
CTRIDA[1:0]
AF_NOA[8:0]
RATEA[2:0]
ASXA
DEL1-2A[25:0]
December 2009
Description
Ch5-8 synchronization. When set HIGH, the "asx"
bit of the audio control packet RATE word
designates audio channels 5 to 8 as
asynchronous, as per SMPTE 299M. When set
LOW, the "asx" bit of the audio control packet
RATE word designates synchronous audio.
Ch5/6 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 5 and 6.
Ch7/8 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 7 and 8.
Ch5-8 reserve words. Designates the value set in
the RSRV words of the audio control packet for
audio channels 5 to 8, as per SMPTE 299M.
Not used.
Ch1-4 audio control packet demultiplex enable.
When set HIGH, the audio control packets in the
Luma channel of the video data stream for audio
channels 1 to 4 will be demultiplexed.
Ch1-4 audio control packet DID setting.
Designates the audio control packet DID for
audio channels 1 to 4. See
setting is audio group 1.
Ch1-4 audio frame number. Designates the audio
frame number for audio channels 1 to 4.
Ch1-4 sampling frequency. Designates the audio
sampling frequency for audio channels 1 to 4,
taken from the RATE word of the audio control
packet as defined in SMPTE 299M.
Ch1-4 synchronization. When set HIGH, the "asx"
bit of the audio control packet RATE word
designates audio channels 1 to 4 as
asynchronous, as per SMPTE 299M. When set
LOW, the "asx" bit of the audio control packet
RATE word designates synchronous audio.
Ch1/2 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 1 and 2.
Table
5-24. The default
Address
02A
02D
023
024
025
026
027
028
029
02B
02C
02E
02F
02F
030
031
032
032
033
034
035
036
02F
Bit
1-0
7-0
7-0
7-0
1-0
7-0
7-0
7-0
1-0
7-0
7-0
7-3
1-0
7-0
3-1
1-0
7-0
7-0
7-0
0
2
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
Default
11b
81 of 90
0
0
0
0
0
1
0
0
0
0