GS1503BCVE2 GENNUM [Gennum Corporation], GS1503BCVE2 Datasheet - Page 43

• Manufacturer Part Number: GS1503BCVE2
• Description: HD Embedded Audio CODEC Data Sheet
• Manufacturer: GENNUM [Gennum Corporation]

4.11.2 Arbitrary Data Multiplexing in Host Interface Mode
To select this mode, set ARBITMODE bit 0 in Host Interface register 050h HIGH. In this
mode, the DID, SDID, DC and User Data Words must be programmed via the
corresponding Host Interface registers. Set the video line number for field 1 and field 2
in which the arbitrary data packets are to be multiplexed using the ARBITLINEA[11:0]
and ARBITLINEB[11:0] Host Interface registers respectively. The arbitrary data packet is
multiplexed when ARBITON bit 1 in Host Interface register 050h is set HIGH. ARBITON
should be set LOW during the programming of the arbitrary data packet in the Host
Interface.
ARBITLINEA[11:0] and ARBITLINEB[11:0] should not be set to the two line numbers
following the line number set in the SW_LNA[12:0] and SW_LNB[12:0] Host Interface
registers. For example, with the default setting of line 7 field 1, ARBITLINEA[11:0]
should not be set to line 8 or 9.
Table 4-32: Register Settings
Table 4-33: Multiplex Mode Host Interface Registers
GS1503B HD Embedded Audio CODEC
Data Sheet
37953 - 1
Name
ARBITON
ARBITMODE
ARBITDID[7-0]
ARBITSDID[7-0]
ARBITDC[7-0]
ARBITLINEA[11:0]
ARBITLINEB[11:0]
ARBITUDW
Control
Item
Video
VIDEO_DET
December 2009
VM_SEL
Name
Description
Arbitrary packet multiplex enable (1: Enabled)
Valid only when ARBITMODE is HIGH
Arbitrary packet mode selection
(0: External pin mode; 1: Host mode)
Arbitrary packet DID setting
Arbitrary packet SDID setting
Arbitrary packet DC setting
Field 1 multiplexing line
Field 2 multiplexing line
Arbitrary packet UDW setting
Description
Video input format (external pin/internal
register) configuration select. When set LOW,
the video input format is configured via the
VM[3:0] pins. When set HIGH, the video input
format is configured via the "VM[3:0]" bits.
Video signal detection flag. Set HIGH when 3
consecutive TRS are detected in the input video
signal.
Address
100-1FE
050
050
051
052
053
054
055
056
057
Address
000
000
Bit
7-0
7-0
7-0
3-0
7-0
3-0
7-0
7-0
1
0
Bit
7
6
Setting
R/W
1
1
–
–
–
–
–
–
R/W
R
Default
Default
43 of 90
0
0
0
0
0
0
0
0
0
0