GS1503B Gennum Corporation, GS1503B Datasheet
GS1503B
Related parts for GS1503B
GS1503B Summary of contents
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... Description The GS1503B is a highly integrated, single chip solution for embedding/extracting digital audio streams into and out of high definition digital video signals. The GS1503B supports insertion/extraction of 24-bit synchronous audio data with a 48kHz sample rate. Audio signals with different sample rates may be converted to 48kHz by using audio sample rate converters before or after the GS1503B ...
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... ANCI Arbitrary Generation Packet Demux Control Packet Demux Audio Packet Demux Demultiplex Mode Block Diagram Proprietary and Confidential 37953 - 0 GS1503B Data Sheet EXTH EXTF SCRBYPASS TRS CRC Inserter & Inserter Scrambler HOST INTERFACE HOST INTERFACE SCRBYPASS CRC Inserter & 20 Scrambler ...
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... Digital Audio Input Timing....................................................................29 4.6.3 Audio Clock Phase Locked Loop .........................................................31 4.6.4 Audio Signal Input Detection ...............................................................31 4.6.5 Audio Channel Status CRC Error Detection ........................................32 4.6.6 Audio Input Parity Error Detection .......................................................32 4.6.7 Audio Channel Status CRC Insert Function ........................................33 4.7 Audio Data Packets ......................................................................................33 Proprietary and Confidential 37953 - 0 GS1503B Data Sheet August 2006 ...
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... Audio Control Packet DID Setting........................................................68 5.9 Arbitrary Data Packets ..................................................................................70 5.9.1 Arbitrary Data Demultiplexing in External Pin Mode ............................71 5.9.2 Arbitrary Data Demultiplexing in Host Interface Mode .........................71 5.10 Ancillary Data Deletion ................................................................................72 5.10.1 Entire Ancillary Data Deletion ............................................................72 5.10.2 Audio Group Designation Ancillary Data Deletion .............................72 Proprietary and Confidential 37953 - 0 GS1503B Data Sheet August 2006 ...
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... Demultiplex Mode With Word Clock Input ..................................................73 6. Using the GS1503B with the GS4911B or GS4910B..............................................85 7. References & Bibliography......................................................................................86 8. Packaging & Ordering Information ..........................................................................87 8.1 Package Dimensons .....................................................................................87 8.2 Packaging Data .............................................................................................87 8.3 Ordering Information .....................................................................................87 9. Revision History ......................................................................................................88 Proprietary and Confidential 37953 - 0 GS1503B Data Sheet August 2006 ...
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... VIN0 135 CPU_SEL 136 AM1 137 AM0 138 VM3 139 VM2 140 VM1 141 VM0 142 RESET 143 GND 144 GS1503B TOP VIEW Proprietary and Confidential 37953 - 0 GS1503B Data Sheet ...
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... Audio clock PLL control signal for channels Cascade mode select. When set HIGH, the GS1503B will default to audio groups 3 and 4. Two GS1503B devices can then be cascaded in series to allow channels of audio to be multiplexed or demultiplexed (only one device requires CASCADE to be set HIGH). ...
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... TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a horizontal sync signal can be input to the device for TRS and line number insertion. Field sync signal. The GS1503B outputs a field sync signal derived from the incoming TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a field sync signal can be input to the device for TRS and line number insertion ...
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... Audio signal output for channels 7 and 8. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. Demultiplex Mode select. Valid in Demultiplex Mode only. When set HIGH, the GS1503B requires a 48kHz word clock input at WCINA and WCINB. This word clock must be synchronous to the word clock used to embed the audio data ...
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... RESET I Description Host Interface mode select. When set HIGH, the GS1503B is configured for Host Interface Mode A. When set LOW, the GS1503B is configured for Host Interface Mode B. Audio format select. In Multiplex Mode, AM[1:0] indicates the input audio data format. Demultiplex Mode, AM[1:0] indicates the output audio data format. AM[1] is the MSB and AM[0] is the LSB ...
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... TTL Level IH V TTL Level 1MHz 1MHz 1MHz Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Value -0.3V to 4.0V -0.3 to 5.5V 0°C to 70°C -65°C to 150°C 260°C Min Typ Max Units 3.0 3.3 3.6 270 -1 – – -0.4 – ...
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... AOH t – RESET – Multiplexer Mode Demultiplexer Mode t VS VCLK Data* * VIN[19:0], EXTF, EXTH, PKTEN, PKT[7:0] Figure 2-1: Video Data Input Setup & Hold Time Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Min Typ Max Units – 74.25 80 5.0 – – 5.0 – – 3.5 – ...
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... Figure 2-3: Audio Data Input Setup & Hold Time ACLKA/B Data* * AOUT1/2, AOUT3/4, AOUT5/6, AOUT7/8 Figure 2-4: Audio Data Output Delay & Hold Time VDD(min) VDD RESET Figure 2-5: Reset Timing Proprietary and Confidential GS1503B Data Sheet t VOH t VOD AOH t AOD t RESET 37953 - 0 August 2006 ...
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... Figure 2-7: Standard Eutectic Solder Reflow Profile Proprietary and Confidential 37953 - 0 GS1503B Data Sheet 60-150 sec. 10-20 sec. 3˚C/sec max 6 min. max 60-150 sec. 20-40 sec. 3˚C/sec max August 2006 6˚ ...
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... Write Address Setup Time Write Data Setup Time Write Data Hold Time Read Cycle 1 Address 2 CPUCS CPURE 3 CPUWE 4 Figure 3-1: Host Interface Mode A Timing (CPU_SEL set HIGH) Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Number Min Typ Max 1 50 – – – 4 – ...
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... Write Cycle Time Write Enable Setup Time Write Address Setup Time Write Chip Select Setup Time Write Chip Select Hold Time Write Data Setup Time Write Data Hold Time Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Number Min Typ Max 1 80 – – ...
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... Upper Address CPUDAT[7:0] CPUCS CPUWE Figure 3-3: Host Interface Mode B Write Cycle Timing (CPU_SEL set LOW) Table 3-4: Host Interface Mode B Control Codes CPUADR[1: Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Write Lower Address Data ...
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... Host Interface or using dedicated external pins maximum of 255 8-bit words can be multiplexed (excluding Ancillary Data Flags and Checksum). To use the GS1503B in Multiplex Mode, set the MUX/DEMUX external pin LOW. Proprietary and Confidential 37953 - 0 GS1503B Data Sheet ...
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... The video standard is selected from the VM[3:0] external pins or VM[3:0] bits 3-0 in Host Interface register 000h. To configure the video standard via the Host Interface, VM_SEL bit 7 in Host Interface register 000h must be set HIGH. The GS1503B will default to the VM[3:0] external pin setting. The supported video standards are listed in Table 4-1 ...
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... [9:0] VIN[9:0] +3.3V DSCBYPASS Figure 4-1: Configuration for 10-bit Y and C Numbers SAV Figure 4-2: Video Input Format 10-bit with TRS and Line Numbers Proprietary and Confidential 37953 - 0 GS1503B Data Sheet EXTF EXTH /C Input Video with TRS and Line b r Video Address Bit Setting ...
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... [9:0] VIN[9:2] VIN[1:0] +3.3V DSCBYPASS Figure 4-3: Configuration for 8-bit Y and C Numbers SAV Figure 4-4: Video Input Format 8-bit with TRS and Line Numbers Proprietary and Confidential 37953 - 0 GS1503B Data Sheet EXTF EXTH /C Input Video with TRS and Line b r Video Address Bit Setting ...
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... Input Without TRS and Line Numbers b r The GS1503B will insert TRS and Line Numbers based on EXTF and EXTH inputs. See Figure 4-6 for timing. In progressive format video standards, a high-to-low edge signal must be input at the EXTF external pin on every frame to indicate the position of line 1 ...
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... EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling GS1503B Y [19:0] VIN[19:0] DSCBYPASS Figure 4-8: Configuration for 20-bit Scrambled Input Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit Setting 001 3 1 001 001 0 1 Address ...
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... Y and GS1503B VOUT[19:0] SCRBYPASS Figure 4-9: Configuration for 20-bit Scrambled Output Output r GS1503B VOUT[19:10] VOUT[9:0] +3.3V SCRBYPASS Figure 4-10: Configuration for 10-bit Y and C Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Y [19:0] Address Bit Setting 001 2 0 Y[9: [9:0] /C Output b r August 2006 Default 0 ...
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... TRS are detected in the input video signal. Also, the VIDEO_DET bit of Host Interface register 000h is set HIGH. The GS1503B will set the CRC_ERR external pin HIGH when a CRC error is detected in the input video signal. Also, the CRC_ERR bit 5 of Host Interface register 000h is set HIGH ...
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... Illegal code re-mapping (1: Enabled) 4.5.5 Input Blanking When the CRC_INS bit 4 of Host Interface register 000h is set HIGH, the GS1503B will re-calculate the video line CRC words. The re-calculated CRC words are inserted in the video output signal. When CRC_INS is set LOW, the line CRC words are not updated and existing CRC words at the input of the device will be output unchanged ...
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... TRS_INS TRS word insertion (1: Enabled) Address When LN_INS bit 1 of Host Interface register 008h is set HIGH, the GS1503B will insert line numbers into the video data stream. When set LOW, existing line numbers will remain in the output video stream. When EXT_SEL bit 3 of Host Interface register 001h is set HIGH, line numbers will be inserted based on the timing of EXTH and EXTF input signals ...
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... LSB 0 MODE1 MODE2 Sync Preamble (AES/EBU) The GS1503B will accept two audio input formats, AES/EBU digital audio input and serial input, as listed in Table 4-16. Serial input can be formatted in the following two modes. See Figure 4-11. • 24-bit Left Justified; MSB first • ...
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... Y [19:0] Audio Channels 1 & 2 Audio Channels 3 & 4 6.144MHz (128 fs) Audio Channels 5 & 6 Audio Channels 7 & 8 6.144MHz (128 fs) 6.144MHz Figure 4-12: AES/EBU Input Configuration and Timing Proprietary and Confidential 37953 - 0 GS1503B Data Sheet GS1503B VIN[19:0] AIN1/2 AIN3/4 ACLKA WCINA AIN5/6 AIN7/8 ACLKB WCINB ...
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... WCINA/B AIN1/2, AIN3/4 AIN5/6, AIN7/8 A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. The GS1503B divides this clock clock the 3.072MHz audio data. An audio word clock at 48kHz (fs) must also be supplied to the WCINA and WCINB inputs, as shown in Figure 4-13 ...
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... The audio input signal detect registers will be set HIGH in AES/EBU audio mode when the preamble of the audio input data is detected 3 times consecutively. In serial audio input mode, the GS1503B will set the audio input signal detect registers HIGH when a 48kHz word clock is detected at the corresponding inputs. ...
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... Host Interface register 011h will be set HIGH. In serial audio input mode, the CRC error flags are always set LOW. In AES/EBU audio mode, the GS1503B will check for Audio Parity errors. If any Audio Parity errors are detected in an AES/EBU audio input channel pair, the corresponding bit in Host Interface register 012h will be set HIGH ...
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... Audio Data Packets 4.7.1 Audio Data Packet Structure When bits 7-4 of Host Interface register 011h are set HIGH, the GS1503B will re-calculate the Channel Status CRC word for the corresponding audio input channel pair. The re-calculated Channel Status CRC word is multiplexed into the audio data packet as per SMPTE 299M ...
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... Host Interface register 014h. Table 4-23 the corresponding audio group DID. When CASCADE is set LOW (external pin or register), the GS1503B will default to audio groups 1 and 2, where AIN1/2 and AIN3/4 will be multiplexed with audio group 1 DID, and AIN5/6 and AIN7/8 with audio group 2 DID. ...
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... Ch2 multiplex enable (1: Enabled) CHACT0 Ch1 multiplex enable (1: Enabled) When CASCADE is set HIGH (external pin or register), the GS1503B will default to audio groups 3 and 4, where AIN1/2 and AIN3/4 will be multiplexed with audio group 3 DID, and AIN5/6 and AIN7/8 with audio group 4 DID. ...
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... SW_LNB[12:0] Video Field 2 switching point setting The video switching point for field 1 and field 2 can be configured via the GS1503B Host Interface. The SW_LNA[12:0] register is used to configure the video switching line for field 1, and SW_LNB[12:0] to set video switching line for field 2. In progressive format video standards, only the SW_LNA[12:0] register is used ...
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... To configure the GS1503B for cascade mode, the CASCADE external pin or CASCADE bit 7 of Host Interface register 014h is set HIGH. When set HIGH, the GS1503B will default to audio groups 3 and 4. When set LOW, the GS1503B will default to audio groups 1 and 2. GS1503B ...
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... Video Signal after GS1503B Insertion of Audio Groups 1 & 2 (CASCADE = 0) Figure 4-17: Insertion of Audio Groups 1 & 2, without / with existing packets) Video Signal before GS1503B (with existing Audio Data Packets) Video Signal after GS1503B Insertion of Audio Groups 3 & 4 (CASCADE = 1) Figure 4-18: Insertion of Audio Groups 3 & Cascade mode Proprietary and Confidential ...
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... Figure 4-19. Blank (200 h ) Video Signal after GS1503B Insertion of Audio Groups 3 & 4 (CASCADE = 1) Figure 4-19: Insertion of Audio Groups 3 & 4 with space between EAV and audio Figure 4-20 shows the structure of the audio control packet as defined in SMPTE 299M. An audio control packet is multiplexed once per field in the Luma channel of the video data stream ...
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... Table 4-30 corresponding audio control packet group DID. When CASCADE is set LOW (external pin or register), the GS1503B will default to audio groups 1 and 2, where the audio control packet for AIN1/2 and AIN3/4 will be multiplexed with group 1 DID, and AIN5/6 and AIN7/8 with group 2 DID. ...
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... Ch5-8 Sampling frequency data Table 4-30: Audio Control Packet Group DID Host Interface Settings Audio Group 10-bit Data 1 1E3h 2 2E2h 3 2E1h 4 1E0h Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Host Interface Register Setting (2-bit) 11b 10b 01b 00b Address Bit Setting 02F 2 1 02F ...
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... The GS1503B can multiplex arbitrary data packets according to SMPTE 291M. Typically, this consists of linear time code (LTC), vertical interval time code (VITC) or other user data, which is multiplexed once per video field. The GS1503B has two modes in which arbitrary data can be multiplexed into the Luma channel of the video data stream ...
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... PKT[7:0] Arbitrary Packet This is the default mode for multiplexing arbitrary data packets. The GS1503B will set the PKTENO external pin HIGH when arbitrary data can be input to the device. Two VCLK cycles after PKTENO goes HIGH, the user should set the PKTEN arbitrary packet enable pin HIGH ...
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... ARBITLINEA[11:0] and ARBITLINEB[11:0] should not be set to the two line numbers following the line number set in the SW_LNA[12:0] and SW_LNB[12:0] Host Interface registers. For example, with the default setting of line 7 ARBITLINEA[11:0] should not be set to line Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit Setting 050 1 ...
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... HIGH. EXT_SEL External EXTH/EXTF input select. When set LOW, the EXTH and EXTF pins are configured as outputs. When set HIGH, the GS1503B will insert TRS and Line Numbers based on signals input at the EXTH and EXTF pins. SCRBYPASS Scramble processing bypass select. When set HIGH, the internal scrambler and NRZ(I) encoder is bypassed ...
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... LN_INS and TRS_INS must be set LOW. LN_INS Line insertion enable. When set HIGH, the GS1503B will insert line numbers into the video data stream. When set LOW, existing line numbers will remain in the output video stream. TRS_INS TRS insertion enable. When set HIGH, the GS1503B will insert TRS codes into the video data stream ...
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... AP1/2_ERR Ch1/2 audio parity error detection. When set HIGH, an audio parity error has been detected in the Ch1/2 audio input. Valid only when AES/EBU audio input format is selected. Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit R/W Default 011 6 R/W ...
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... CASCADE Cascade select. When set HIGH, the GS1503B will default to audio groups 3 and 4. When set LOW, the GS1503B will default to audio groups 1 and 2. NOTE: The status of the CASCADE external pin is not updated in this register. The value programmed in this register is logical OR'd with the CASCADE external pin setting ...
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... Ch1-4 audio control packet multiplex enable. When set HIGH, the audio control packets for audio channels will be multiplexed into the Luma channel of the video data stream. Table 4-30. The default Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit R/W Default 020 7-3 – ...
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... LSBs of the arbitrary data packet DID word. The 2 MSBs are internally generated. "ARBITDID[7]" is the MSB and "ARBITDID[0]" is the LSB. Valid only when "ARBITMODE" is HIGH. Table 4-30. The default Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit R/W Default 02F 1-0 R/W 030 ...
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... User Data Words. The 2 MSBs are internally ARBITUDW254 generated. Valid only when "ARBITMODE" is HIGH. Table 4-34: Audio Channel Status Default Values Address Value 058 85 059 08 05A 2C Others 00 Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit R/W 052 7-0 R/W 053 7-0 R/W 054 3-0 R/W 055 7-0 056 3-0 R/W 057 ...
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... Host Interface registers maximum of 255 8-bit words can be demultiplexed (excluding Ancillary Data Flags and Checksum). To use the GS1503B in Demultiplex Mode, set the MUX/DEMUX external pin HIGH. Proprietary and Confidential 37953 - 0 ...
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... The video standard is selected from the VM[3:0] external pins or VM[3:0] bits 3-0 in Host Interface register 000h. To configure the video standard via the Host Interface, VM_SEL bit 7 in Host Interface register 000h must be set HIGH. The GS1503B will default to the VM[3:0] external pin setting. The supported video standards are listed in Table 5-1 ...
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... EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling GS1503B Y [19:0] VIN[19:0] DSCBYPASS Figure 5-1: 20-bit Scrambled Input Configuration Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit Setting 001 3 0 001 1 0 001 0 0 August 2006 ...
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... [9:0] VIN[9:0] +3.3V DSCBYPASS Figure 5-2: 10-bit Y and Figure 5-3: Video Input Format (10-bit with TRS and Line Numbers) Proprietary and Confidential 37953 - 0 GS1503B Data Sheet EXTF EXTH Input with TRS and Line Numbers Configuration Video Address Bit Setting 001 3 0 001 ...
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... Scrambled Output Output r GS1503B VOUT[19:10] VOUT[9:0] +3.3V SCRBYPASS Figure 5-4: 10-bit Y and GS1503B VOUT[19:0] SCRBYPASS Figure 5-5: 20-bit Scrambled Output Configuration Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Y[9: [9:0] Output Configuration Address Bit Setting 001 [19:0] August 2006 Default ...
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... TRS are detected in the input video signal. Also, the VIDEO_DET bit of Host Interface register 000h is set HIGH. The GS1503B will set the CRC_ERR external pin HIGH when a CRC error is detected in the input video signal. Also, the CRC_ERR bit 5 of Host Interface register 000h is set HIGH ...
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... Address When LN_INS bit 1 of Host Interface register 008h is set HIGH, the GS1503B will insert line numbers into the video data stream. When set LOW, existing line numbers will remain in the output video stream. ...
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... Register setting AM[1:0] Audio output format selection (AM[1] is MSB) When TRS_INS bit 0 of Host Interface register 008h is set HIGH, the GS1503B will insert TRS codes into the video data stream. When set LOW, existing TRS codes will remain in the output video stream. Address ...
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... The CH_SEL[2:0] setting for audio channel 1 is 000b, through to 111b for channel 8. The CS_RQST bit must be set HIGH to begin the process of extracting the Audio Channel Status information. Once extracted, the GS1503B will set CS_WEND bit HIGH and the user can access the data for Host Interface registers 058h to 06Eh ...
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... Audio Channel Status select ACLKA/B AOUT1/2, AOUT3/4 AOUT5/6, AOUT7/8 Y [19:0] VIN[19:0] 6.144MHz (128 fs) ACLKA 6.144MHz (128 fs) ACLKB 6.144MHz Figure 5-7: AES/EBU Audio Output Configuration and Timing Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit Setting 06F 5 – 06F 4 1 06F 3 1 06F 2-0 – ...
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... The CS_RQST bit must be set HIGH to begin the process of extracting the Audio Channel Status information. Once extracted, the GS1503B will set CS_WEND bit HIGH and the user can access the data for Host Interface registers 058h to 06Eh. When DEC_MODE (external pin or register setting) is set LOW, the audio word clock inputs WCINB and WCINB should be grounded ...
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... Audio Clock Phase Locked Loop Y [19:0] Figure 5-9 shows the configuration for deriving the 6.144MHz audio clock in AES/EBU and serial audio output modes. The GS1503B will internally synchronize the audio output to the corresponding ACLK. This configuration is not required when DEC_MODE is set HIGH. 6.144MHz (128 fs) ...
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... The number of audio data packets corrected in one video frame will be reported in the corresponding Host Interface registers CORRECTA[11:0] and CORRECTB[11:0]. The GS1503B will also report the number of audio data packets which could not be corrected in one video frame in the corresponding Host Interface registers NO_CORRECTA[11:0] and NO_CORRECTB[11:0]. ...
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... DATAIDB[1:0] is discontinuous, the DBNB_ERR bit 7 of Host Interface register 015h will be set HIGH. The GS1503B will check the parity (bit 8) for the CLK, CH1-4 and ECC0-5 words in the embedded audio data packets. When a parity bit error is detected in audio data packets with audio group DID set in DATAIDA[1:0], the ADPB8A_ERR bit 2 of Host Interface register 015h will be set HIGH ...
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... Host Interface register 014h. setting for the corresponding audio group DID. When CASCADE is set LOW (external pin or register), the GS1503B will default to audio groups 1 and 2, where AOUT1/2 and AOUT3/4 will be demultiplexed from audio data packets with group 1 DID, and AOUT5/6 and AOUT7/8 will be demultiplexed from audio data packets with group 2 DID ...
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... To configure the GS1503B for cascade mode, the CASCADE external pin or CASCADE bit 7 of Host Interface register 014h is set HIGH. When set HIGH, the GS1503B will default to audio groups 3 and 4. When set LOW, the GS1503B will default to audio groups 1 and 2. GS1503B ...
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... Table 5-24 corresponding audio control packet group DID. When CASCADE is set LOW (external pin or register), the GS1503B will default to audio groups 1 and 2, where audio control packet data for channels will be demultiplexed from packets with group 1 DID, and audio control packet data for channels will be demultiplexed from packets with group 2 DID ...
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... Ch5-8 Sampling frequency data Table 5-24: Audio Control Packet Group DID Host Interface Settings Audio Group 10-bit Data 1 1E3h 2 2E2h 3 2E1h 4 1E0h Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Host Interface Register Setting (2-bit) 11b 10b 01b 00b Address Bit Setting 02F 2 1 02F ...
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... Typically, arbitrary data packets consist of linear time code (LTC), vertical interval time code (VITC) or other user data, which is multiplexed once per video field. The GS1503B has two modes in which arbitrary data can be demultiplexed from the Luma channel of the video data stream. A maximum of 255 user data words can be demultiplexed ...
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... Packet 5.9.2 Arbitrary Data Demultiplexing in Host Interface Mode This is the default mode for demultiplexing arbitrary data packets. The GS1503B will set the PKTEN external pin HIGH before arbitrary data will be output. Two VCLK cycles after PKTEN goes HIGH, arbitrary data is output on the PKT[7:0] bus. ...
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... Entire Ancillary Data Deletion 5.10.2 Audio Group Designation Ancillary Data Deletion The GS1503B can be configured to delete the embedded ancillary data packets, after demultiplexing. There are two modes for ancillary data deletion. When the ANCI external pin or ANCI bit 1 of Host Interface register 040h is set HIGH, all ancillary data packets in both the Luma and Chroma channel of the input video stream are deleted ...
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... WCOUTA and WCOUTB pins in serial audio output modes. If the GS1503B used in conjunction with a HD audio module, which encodes audio clock phase information incorrectly, the DEC_MODE external pin or DECMODE bit 2 of Host Interface register 01Eh must be set HIGH. When HIGH, an audio word clock synchronous to the original word clock used for embedding must be input at the WCINA and WCINB pins ...
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... Figure 5-13: Demultiplex Mode with 48kHz Word Clock Input System Example Figure 5-14 shows the timing relationship between the audio word clock inputs and word clock outputs when the GS1503B is configured to serial audio output mode. 1 CLK Figure 5-14: WCINA/B Input to WCOUTA/B Output Timing Diagram ...
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... HIGH. EXT_SEL External EXTH/EXTF input select. When set LOW, the EXTH and EXTF pins are configured as outputs. When set HIGH, the GS1503B will insert TRS and Line Numbers based on signals input at the EXTH and EXTF pins. SCRBYPASS Scramble processing bypass select. ...
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... OR'd with the DEC_MODE external pin setting. MUXERRB Ch5-8 audio sample clock error. When set HIGH, the GS1503B is unable to recover the audio clock phase data in the embedded audio data packet for audio channels See MUXERRA Ch1-4 audio sample clock error. When set HIGH, ...
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... Valid only when "CS_MODE" is set HIGH. CS_RQST Audio Channel Status request. When set HIGH, the GS1503B will read and store the Audio Channel Status information from the audio channel set in Host Interface register "CH_SEL[2:0]". Valid only when "CS_MODE" is set HIGH. ...
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... CASCADE Cascade select. When set HIGH, the GS1503B will default to audio groups 3 and 4. When set LOW, the GS1503B will default to audio groups 1 and 2. NOTE: The status of the CASCADE external pin is not updated in this register. The value programmed in this register is logical OR'd with the CASCADE external pin setting ...
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... Ch1-4 ECC correctable packets. Designates the number of audio data packets for channels [11:0] that have been corrected in one video frame using the BCH forward error correction system. 5-19. When CASCADE (external pin or Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit R/W 014 1-0 R/W 015 ...
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... RATE word designates synchronous audio. DEL1-2B[25:0] Ch5/6 delay data. Designates the accumulated audio processing delay relative to video for audio channels 5 and 6. Table 5-24. The default setting is audio Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit R/W 01C 3-0 R 01D 7-0 020 ...
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... RSRVA[17:0] Ch1-4 reserve words. Designates the value set in the RSRV words of the audio control packet for audio channels per SMPTE 299M. Table 5-24. The default setting is audio Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit R/W 028 1-0 R/W 029 7-0 ...
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... Audio group 2 control packet delete. When set HIGH, all audio control packets with group 2 DID will be deleted from the Luma video data stream. Valid only when "DEL_SEL" is HIGH fixed. Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit R/W 040 7-2 – ...
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... LSB. Valid only when "ARBITMODE" is HIGH. ARBITLINEB Field 2 arbitrary packet demultiplex line number setting. Designates the field 2 video line from which [11:0] the arbitrary data packets will be demultiplexed. Valid only when "ARBITMODE" is HIGH. Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit R/W 041 0 R/W 042 7-0 R/W ...
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... Arbitrary packet User Data Word. Designates the 8 LSBs for up to 255 arbitrary packet User Data : Words. Arbitrary data can be read from these ARBITUDW254 registers once "ARBITON" has been set HIGH to LOW. Valid only when "ARBITMODE" is HIGH. Proprietary and Confidential 37953 - 0 GS1503B Data Sheet Address Bit R/W 056 3-0 R/W 057 7-0 ...
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... In Serial Audio multiplex mode, the GS4911B or GS4901B can be used to provide clocks for the input audio. Figure 6-1 Audio Chain Figure 6-1: Using the GS1503B with the GS4911B or GS4910B in Serial Audio Mode Proprietary and Confidential 37953 - 0 GS1503B Data Sheet shows this arrangement. Video Data VIN[19:0] PCLK (74 ...
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... EBU Tech. 3250-E Specification of the Digital Audio Interface (The AES/EBU Interface) (Second Edition 1992) Society of Motion Picture and Television Engineers: http://www.smpte.org Audio Engineering Society: http://www.aes.org European Broadcast Union: http://www.ebu.ch Proprietary and Confidential 37953 - 0 GS1503B Data Sheet August 2006 ...
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... Moisture Sensitivity Level Junction to Case Thermal Resistance, θ Junction to Air Thermal Resistance, θ Pb-free and RoHS Compliant Part Number Package GS1503BCVE2 144 pin TQFP Proprietary and Confidential 37953 - 0 GS1503B Data Sheet 72 18.0 ± 0.4 16.0 ± 0 1.20 MAX 144 pin TQFP Dimensions in millimetres Value ...
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... Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. © Copyright 2006 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com Proprietary and Confidential 37953 - 0 88 GS1503B Data Sheet Changes / Modifications New document. August 2006 ...