GS1503BCVE2 GENNUM [Gennum Corporation], GS1503BCVE2 Datasheet - Page 29

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GS1503BCVE2

Manufacturer Part Number
GS1503BCVE2
Description
HD Embedded Audio CODEC Data Sheet
Manufacturer
GENNUM [Gennum Corporation]
Datasheet
4.6.2.2 Serial Audio Input Modes
A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. The
GS1503B divides this clock by 2 to clock the 3.072MHz audio data. An audio word clock
at 48kHz (fs) must also be supplied to the WCINA and WCINB inputs, as shown in
Figure
used to enter the 23 8-bit bytes of the Audio Channel Status Block, as defined in
AES3-1992. NOTE: The CRC byte is generated internally by the GS1503B. The GS1503B
will default to Professional audio mode with 24-bit word length and emphasis off. See
Table
Figure 4-13: Serial Audio Input Configuration and Timing
GS1503B HD Embedded Audio CODEC
Data Sheet
37953 - 1
AIN1/2, AIN3/4
AIN5/6, AIN7/8
ACLKA/B
WCINA/B
4-34.
4-13. The AUDIO_CS[183:0] bits in Host Interface registers 058h to 06Eh can be
December 2009
Y/C b / C r [19:0]
Audio Channels 1 & 2
Audio Channels 3 & 4
6.144MHz (128 fs)
48kHz (fs)
Audio Channels 5 & 6
Audio Channels 7 & 8
6.144MHz (128 fs)
48kHz (fs)
64 CLKs
VIN[19:0]
AIN1/2
AIN3/4
ACLKA
WCINA
AIN5/6
AIN7/8
ACLKB
WCINB
GS1503B
64 CLKs
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