GS1503BCVE2 GENNUM [Gennum Corporation], GS1503BCVE2 Datasheet - Page 30

• Manufacturer Part Number: GS1503BCVE2
• Description: HD Embedded Audio CODEC Data Sheet
• Manufacturer: GENNUM [Gennum Corporation]

4.6.3 Audio Clock Phase Locked Loop
Figure 4-14
audio input mode. The GS1503B will internally synchronize the AES/EBU audio input to
the corresponding ACLK, using the clock extracted from the AES/EBU bi-phase mark
encoding. This configuration is not required for serial audio input modes.
Figure 4-14: Block Diagram of GS1503B Audio Clock PLL
4.6.4 Audio Signal Input Detection
The audio input signal detect registers will be set HIGH in AES/EBU audio mode when
the preamble of the audio input data is detected 3 times consecutively. In serial audio
input mode, the GS1503B will set the audio input signal detect registers HIGH when a
48kHz word clock is detected at the corresponding inputs. Audio channels 1 to 4 will be
set when WCINA is validated, and audio channels 5 to 8 when WCINB is validated. Host
Interface register 010h, bits 6-3, report the individual audio channels pairs detected.
Table 4-18: Register Settings
GS1503B HD Embedded Audio CODEC
Data Sheet
37953 - 1
Y/C b / C r [19:0]
Audio Channels 1 & 2
Audio Channels 3 & 4
Audio Channels 5 & 6
Audio Channels 7 & 8
Name
AUD7/8_DET
AUD5/6_DET
shows the configuration for deriving the 6.144MHz audio clock in AES/EBU
December 2009
Description
Ch7/8 Audio input signal detection (1:Detection)
Ch5/6 Audio input signal detection (1:Detection)
VIN[19:0]
AIN1/2
AIN3/4
ACLKA
AIN5/6
AIN7/8
ACLKB
GS1503B
PLLCNTA
PLLCNTB
6.144MHz (128 fs)
6.144MHz (128 fs)
Pass
Filter
Pass
Filter
Low
Low
Address
010
010
24.576MHz
24.576MHz
VCXO
Bit
VCXO
6
5
Setting
–
–
÷ 4
÷ 4
Default
0
0
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