GS1503BCVE2 GENNUM [Gennum Corporation], GS1503BCVE2 Datasheet - Page 8

• Manufacturer Part Number: GS1503BCVE2
• Description: HD Embedded Audio CODEC Data Sheet
• Manufacturer: GENNUM [Gennum Corporation]

Table 1-1: Pin Descriptions (Continued)
GS1503B HD Embedded Audio CODEC
Data Sheet
37953 - 1
Number
71, 70, 69,
67, 66, 65,
63, 62, 61,
59, 58, 57,
55, 54, 53,
51, 50, 49,
47, 46
74
75
76
77
78
79
85
87
81, 82, 83,
89, 94, 93,
92, 91, 90
103, 102,
101, 100,
99, 98, 96,
95
105
106
107
110, 111,
112, 114,
115, 116,
118, 119,
120, 122,
123, 124,
126, 127,
128, 130,
131, 132,
134, 135
Symbol
VOUT[19:0]
WCOUTA
WCOUTB
AOUT1/2
AOUT3/4
AOUT5/6
AOUT7/8
DEC_MODE
VCLK
CPUADR[8:0]
CPUDAT[7:0]
CPUCS
CPURE
CPUWE
VIN[19:0]
December 2009
Type
O
O
O
O
O
O
O
I
I
I
I/O
I
I
I
I
Description
Parallel digital video signal output. VOUT[19] is the MSB and VOUT[0] is the LSB.
48kHz word clock for channels 1 to 4. Valid only when operating in Demultiplex Mode.
48kHz word clock for channels 5 to 8. Valid only when operating in Demultiplex Mode.
Audio signal output for channels 1 and 2. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
Audio signal output for channels 3 and 4. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
Audio signal output for channels 5 and 6. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
Audio signal output for channels 7 and 8. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
Demultiplex Mode select. Valid in Demultiplex Mode only. When set HIGH, the
GS1503B requires a 48kHz word clock input at WCINA and WCINB. This word clock
must be synchronous to the word clock used to embed the audio data. The embedded
audio clock phase information in the ancillary data packet will be ignored. See
Demultiplex Mode With Word Clock Input on page
Video clock signal input.
Host Interface address bus. CPUADR[8] is the MSB and CPUADR[0] is the LSB.
Host Interface Mode B (CPU_SEL set LOW), CPUADR[1:0] are used as the Host Interface
control bus. See
Host Interface data bus. CPUDAT[7] is the MSB and CPUDAT[0] is the LSB.
In Host Interface Mode B (CPU_SEL set LOW), CPUDAT[7:0] are used as the Host
Interface address and data bus.
Chip select for Host Interface. Active LOW.
Read enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set
LOW), this input is not used.
Write enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set
LOW), this input is used as the Host Interface control enable.
Parallel digital video signal input. VIN[19] is the MSB and VIN[0] is the LSB.
Table
3-4.
73.
8 of 90
In