GS1503 Gennum Corporation, GS1503 Datasheet
GS1503
Related parts for GS1503
GS1503 Summary of contents
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... TEMPERATURE alignment. Use the GS1503 with Gennum’s GS1545 or GS1522 for two chip HD SDI receive or transmit solutions. 0°C to 70°C The GS1503 operates from a single 3.3V power supply with 5V tolerant I/O and is packaged in a 144 pin LQFP package. 20 Video Detection & ...
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DSCBYPASS De-scrambler & 20 VIN[19:0] Word Alignment Video Detection & 4 VM[3:0] Synchronization ANCI Timing Generation 9 CPUADR[8:0] Host 8 CPUDAT[7:0] Interface 3 CPUCS, CPUWE, CPURE ABSOLUTE MAXIMUM RATINGS ABSOLUTE MAXIMUM RATINGS ABSOLUTE MAXIMUM RATINGS ABSOLUTE MAXIMUM RATINGS PARAMETER Supply ...
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AC ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS V = 3.3V ± 5 0°C to 70°C unless otherwise shown PARAMETER Video Clock Frequency Video Clock Pulse Width Low Video Clock Pulse Width ...
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VCLK Data* * VOUT[19:0], EXTF, EXTH, PKTEN, PKT[7:0] Fig. 2 Video Data Output Delay & Hold Time ACLKA/B Data* * WCINA, AIN1/2, AIN3/4, WCINB, AIN5/6, AIN7/8 Fig. 3 Audio Data Input Setup & Hold Time ACLKA/B Data* * AOUT1/2, AOUT3/4, ...
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HOST INTERFACE HOST INTERFACE HOST INTERFACE HOST INTERFACE Mode A (CPU_SEL set HIGH) PARAMETER Read Cycle Time Read Chip Select Setup Time Read Address Setup Time Read Data Output Delay Time Read Data Hold Time Write Cycle Time Write Chip ...
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Mode B Read Cycle (CPU_SEL set LOW) PARAMETER Read Address Cycle Time Read Cycle Time Read Enable Setup Time Read Address Setup Time Read Chip Select Setup Time Read Chip Select Hold Time Read Data Output Delay Time Read Data ...
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Mode B Write Cycle (CPU_SEL set LOW) PARAMETER Write Address Cycle Time Write Cycle Time Write Enable Setup Time Write Address Setup Time Write Chip Select Setup Time Write Chip Select Hold Time Write Data Setup Time Write Data Hold ...
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... VIN2 132 VDD 133 VIN1 134 VIN0 135 CPU_SEL 136 AM1 137 AM0 138 VM3 139 VM2 140 VM1 141 VM0 142 RESET 143 GND 144 GS1503 TOP VIEW 8 72 GND 71 VOUT19 70 VOUT18 69 VOUT17 68 VDD 67 VOUT16 66 VOUT15 65 VOUT14 64 GND 63 VOUT13 62 VOUT12 61 ...
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... Audio clock PLL control signal for channels Cascade mode select. When set HIGH, the GS1503 will default to audio groups 3 and 4. Two GS1503 devices can then be cascaded in series to allow channels of audio to be multiplexed or demultiplexed (only one device requires CASCADE to be set HIGH). ...
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... TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a horizontal sync signal can be input to the device for TRS and line number insertion. Field sync signal. The GS1503 outputs a field sync signal derived from the incoming TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a field sync signal can be input to the device for TRS and line number insertion ...
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... Parallel digital video signal input. VIN[19] is the MSB and VIN[0] is the LSB. Host Interface mode select. When set HIGH, the GS1503 is configured for Host Interface Mode A. When set LOW, the GS1503 is configured for Host Interface Mode B. Audio format select. In Multiplex Mode, AM[1:0] indicates the input audio data format. ...
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... VM[3:0] bits 3-0 in Host Interface register 000h. To configure the video standard via the Host Interface, VM_SEL bit 7 in Host Interface register 000h must be set HIGH. The GS1503 will default to the VM[3:0] external pin setting. The supported video standards are listed in Table 2. REFERENCE SMPTE DOCUMENT ...
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... Fig. 10 Video Input Format 10-bit with TRS and Line Numbers Register Settings NAME EXT_SEL 0: EXTH/EXTF output select 1: EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling DESCRIPTION ADDRESS GS1503 VIN[19:10] VIN[9:0] +3.3V DSCBYPASS /C Input Video with TRS and Line Numbers b r SAV DESCRIPTION ADDRESS 13 BIT ...
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... Fig. 12 Video Input Format 8-bit with TRS and Line Numbers Register Settings NAME EXT_SEL 0: EXTH/EXTF output select 1: EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling GS1503 VIN[19:12] VIN[11:10] VIN[9:2] VIN[1:0] DSCBYPASS /C Input Video with TRS and Line Numbers b r SAV DESCRIPTION ...
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... Input without TRS and Line Numbers b r The GS1503 will insert TRS and Line Numbers based on EXTF and EXTH inputs. See Figure 14 for timing. In progressive format video standards, a high-to-low edge signal must be input at the EXTF external pin on every frame to indicate the position of line 1. See Figure 15. ...
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... Register Settings (Default Mode) NAME EXT_SEL 0: EXTH/EXTF output select 1: EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling DESCRIPTION ADDRESS GS1503 VIN[19:0] DSCBYPASS Fig. 16 Configuration for 20-bit Scrambled Input DESCRIPTION ADDRESS 16 BIT SETTING DEFAULT 001 3 1 ...
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... Register Settings NAME SCRBYPASS 0: SMPTE 292M scrambling enabled 1: Bypass SMPTE 292M scrambling GS1503 Y [19:0] VOUT[19:0] SCRBYPASS Fig. 17 Configuration for 20-bit Scrambled Output DESCRIPTION GS1503 VOUT[19:10] VOUT[9:0] SCRBYPASS Fig. 18 Configuration for 10-bit Y and DESCRIPTION ADDRESS 17 ADDRESS BIT SETTING DEFAULT 001 ...
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... Video Output CRC Insertion When the CRC_INS bit 4 of Host Interface register 000h is set HIGH, the GS1503 will re-calculate the video line CRC words. The re-calculated CRC words are inserted in the video output signal. When CRC_INS is set LOW, the line CRC words are not updated and existing CRC words at the input of the device will be output unchanged ...
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... Line number insertion (1: Enabled) DESCRIPTION ADDRESS The blanking function is performed at the output of the GS1503 video data stream. If the HBLK_INS bit is set HIGH, any multiplexed audio will be replaced with blanking codes. ADDRESS 008 When EXT_SEL bit 3 of Host Interface register 001h is set HIGH, line numbers will be inserted based on the timing of EXTH and EXTF input signals ...
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... TRS Word Insertion When TRS_INS bit 0 of Host Interface register 008h is set HIGH, the GS1503 will insert TRS codes into the video data stream. When set LOW, existing TRS codes will remain in the output video stream. Register Settings NAME DESCRIPTION TRS_INS TRS word insertion (1: Enabled) 1 ...
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... See Figure 20 for timing. Y [19:0] Audio Channels 1 & 2 Audio Channels 3 & 4 6.144MHz (128 fs) Audio Channels 5 & 6 Audio Channels 7 & 8 6.144MHz (128 fs) ACLKA/B AIN1/2, AIN3/4 AIN5/6, AIN7/8 GS1503 VIN[19:0] AIN1/2 AIN3/4 ACLKA WCINA AIN5/6 AIN7/8 ACLKB WCINB 6.144MHz Fig. 20 AES/EBU Input Configuration and Timing ...
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... Interface registers 058h to 06Eh can be used to enter the 22 8-bit bytes of the Audio Channel Status Block, as defined in AES3-1992. NOTE: The CRC byte is generated internally by the GS1503. The GS1503 will default to Professional audio mode with 24-bit word length and emphasis off. See Table 9. ...
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... Audio Signal Input Detection The audio input signal detect registers will be set HIGH in AES/EBU audio mode when the preamble of the audio input data is detected 3 times consecutively. In serial audio input mode, the GS1503 will set the audio input signal detect Register Settings NAME AUD7/8_DET ...
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... Ch1/2 Audio Channel Status CRC error detection (1: Detection) 1.6.6 Audio Input Parity Error Detection In AES/EBU audio mode, the GS1503 will check for Audio Parity errors. If any Audio Parity errors are detected in an AES/EBU audio input channel pair, the corresponding bit in Host Interface register 012h will be set HIGH. In serial audio input mode, the Audio Parity error flags are always set LOW ...
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... ECC Protected Fig. 23 Audio Data Packet Structure DESCRIPTION When CASCADE is set LOW (external pin or register), the GS1503 will default to audio groups 1 and 2, where AIN1/2 and AIN3/4 will be multiplexed with audio group 1 DID, and AIN5/6 and AIN7/8 with audio group 2 DID. 25 DATA ...
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... DATAIDB [1-0] Ch5-8 Audio data packet DID setting When CASCADE is set HIGH (external pin or register), the GS1503 will default to audio groups 3 and 4, where AIN1/2 and AIN3/4 will be multiplexed with audio group 3 DID, and AIN5/6 and AIN7/8 with audio group 4 DID. Register Settings (CASCADE set HIGH) ...
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... If the SW_LNA[12:0] and SW_LNB[12:0] registers are programmed with values other Interface. The than lines 7 and 569, the output of the GS1503 is not guaranteed to be compatible with all HD audio demultiplex systems. With non-SMPTE 299M compliant switch line settings, the user should avoid inputting a video data stream to the GS1503, which already contains embedded audio data and control packets ...
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... Video Signal after GS1503 Insertion of Audio Groups 1 & 2 (CASCADE = 0) Video Signal before GS1503 (with existing Audio Data Packets) Video Signal after GS1503 Insertion of Audio Groups 3 & 4 (CASCADE = 1) When CASCADE is set HIGH, the GS1503 will multiplex the audio data and control packets immediately after the existing packets, as shown in Figure 26 ...
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... See Figure 27. Blank (200 h ) Video Signal before GS1503 (with space between EAV and existing Audio Data Packets) Video Signal after GS1503 Insertion of Audio Groups 3 & 4 (CASCADE = 1) 1.10 AUDIO CONTROL PACKETS 1.10.1 Audio Control Packet Structure Figure 28 shows the structure of the audio control packet as defined in SMPTE 299M ...
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... Interface setting for the corresponding audio control packet group DID. When CASCADE is set LOW (external pin or register), the GS1503 will default to audio groups 1 and 2, where the audio control packet for AIN1/2 and AIN3/4 will be multiplexed with group 1 DID, and AIN5/6 and AIN7/8 with group 2 DID ...
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Register Settings NAME CTRONA Ch1-4 Audio control packet multiplex enable (1: Enabled) CTRIDA[1:0] Ch1-4 Audio control packet DID set AF_NOA[8:0] Ch1-4 Audio frame number RATEA[2:0] Ch1-4 Sampling frequency data ASXA Ch1-4 Synchronization (0:Synchronous; 1: Non-synchronous) DEL1-2A[26:0] Ch1/2 Delay data DEL3-4A[26:0] ...
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... The GS1503 can multiplex arbitrary data packets according to SMPTE 291M. Typically, this consists of linear time code (LTC), vertical interval time code (VITC) or other user data, which is multiplexed once per video field. The GS1503 has MSB LSB Contents set in Host Interface registers 1 ...
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Arbitrary Data Multiplexing in Host Interface Mode To select this mode, set ARBITMODE bit 0 in Host Interface register 050h HIGH. In this mode, the DID, SDID, DC and User Data Words must be programmed corresponding Host Interface registers. ...
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... The value programmed in this register is logical OR'd with the SCRBYPASS external pin setting. 8BIT_SEL 8-bit input selection. When set HIGH, the GS1503 will accept an 8-bit input video signal. DSCBYPASS Descramble process bypass select. When set HIGH, the internal SMPTE 292M descrambler is bypassed ...
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... When set LOW, existing line numbers will remain in the output video stream. TRS_INS TRS insertion enable. When set HIGH, the GS1503 will insert TRS codes into the video data stream. When set LOW, existing TRS codes will remain in the output video stream. Audio ...
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... Audio Channel Status set. Valid in Serial Audio Channel Input modes. Used to enter the 22 8-bit bytes of : Status the Audio Channel Status Block, as defined in AUDIO_CS Block AES3-1992. [183:176] NOTE: The CRC byte is generated internally by the GS1503. DESCRIPTION ADDRESS 011 012 058 : 06E 36 BIT R/W ...
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... CASCADE Cascade select. When set HIGH, the GS1503 will default to audio groups 3 and 4. When set LOW, the GS1503 will default to audio groups 1 and 2. NOTE: The status of the CASCADE external pin is not updated in this register. The value programmed in this register is logical OR'd with the CASCADE external pin setting ...
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Table 8: Multiplex Mode Host Interface Registers (Continued) CONTROL NAME ITEM AF_NOB[8:0] Ch5-8 audio frame number. Designates the audio frame number for audio channels Will be multiplexed into the audio control packet as per SMPTE 299M. RATEB[2:0] ...
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Table 8: Multiplex Mode Host Interface Registers (Continued) CONTROL NAME ITEM DEL1-2A[26:0] Ch1/2 delay data. Designates the accumulated audio processing delay relative to video for audio channels 1 and 2. Will be multiplexed into the audio control packet as per ...
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Table 9: Audio Channel Status Default Values ADDRESS VALUE 058 85 Professional; Valid Audio; No Emphasis (manual override disabled); 48kHz Sampling Frequency (manual override disabled). 059 08 Two-Channel Mode (manual override disabled). 05A 2C Maximum Audio Sample Word Length is ...
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... VM[3:0] bits 3-0 in Host Interface register 000h. To configure the video standard via the Host Interface, VM_SEL bit 7 in Host Interface register 000h must be set HIGH. The GS1503 will default to the VM[3:0] external pin setting. The supported video standards are listed in Table 10. . REFERENCE SMPTE DOCUMENT ...
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... Y [19:0] Register Settings (Default Mode) NAME EXT_SEL 0: EXTH/EXTF output select 1: EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling DESCRIPTION ADDRESS GS1503 VIN[19:0] DSCBYPASS Fig. 31 20-bit Scrambled Input Configuration DESCRIPTION ADDRESS 42 BIT SETTING DEFAULT 000 7 1 3-0 ...
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... Fig. 33 Video Input Format (10-bit with TRS and Line Numbers) Register Settings NAME EXT_SEL 0: EXTH/EXTF output select 1: EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling GS1503 VIN[19:10] VIN[9:0] +3.3V DSCBYPASS /C Input with TRS and Line Numbers Configuration b r DESCRIPTION ADDRESS 43 ...
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... SCRBYPASS 0: SMPTE 292M scrambling enabled 1: Bypass SMPTE 292M scrambling GS1503 VOUT[19:10 [9:0] VOUT[9:0] SCRBYPASS Fig. 34 10-bit Y and C /C Output Configuration b r DESCRIPTION ADDRESS GS1503 Y [19:0] VOUT[19:0] SCRBYPASS Fig. 35 20-bit Scrambled Output Configuration DESCRIPTION ADDRESS 44 Y[9:0] BIT SETTING DEFAULT 001 2 1 BIT ...
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... DESCRIPTION ADDRESS The blanking function is performed at the output of the GS1503 video data stream. If the HBLK_INS bit is set HIGH, any embedded audio or control packets will be replaced with blanking codes. The GS1503 will demultiplex data contained in the packets, prior to the blanking function, and output at the corresponding pins ...
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... Line number insertion (1: Enabled) 2.5.6 TRS Word Insertion When TRS_INS bit 0 of Host Interface register 008h is set HIGH, the GS1503 will insert TRS codes into the video data stream. When set LOW, existing TRS codes will remain in the output video stream. Register Settings ...
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... Host Interface, AM_SEL bit 7 in Host Interface register 010h must be set HIGH. The GS1503 will default to the AM[1:0] external pin setting. NOTE: When configured in AES/EBU audio mode, the GS1503 will not output a 48kHz (fs) word clock at the WCOUTA and WCOUTB pins. Register Settings NAME ...
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... The CS_RQST bit must be set HIGH to begin the process of extracting the Audio Channel Status information. Once extracted, the GS1503 will set CS_WEND bit HIGH and the user can access the data for Host Interface registers 058h to 06Eh. ...
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... AOUT5/6, AOUT7/8 The CS_RQST bit must be set HIGH to begin the process of extracting the Audio Channel Status information. Once extracted, the GS1503 will set CS_WEND bit HIGH and the user can access the data for Host Interface registers 058h to 06Eh. When DEC_MODE (external pin or register setting) is set LOW, the audio word clock inputs WCINB and WCINB should be grounded ...
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... Audio Channels 3 & 4 AOUT3/4 Low PLLCNTA Pass Filter Audio Channels 5 & 6 AOUT5/6 Audio Channels 7 & 8 AOUT7/8 Low PLLCNTB Pass Filter 6.144MHz (128 fs) Fig. 39 Block Diagram of GS1503 Audio Clock PLL DESCRIPTION ADDRESS 013 50 VCXO ÷4 24.576MHz VCXO ÷4 24.576MHz BIT SETTING DEFAULT 7 ...
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... DID set in DATAIDB[1:0] is discontinuous, the DBNB_ERR bit 7 of Host Interface register 015h will be set HIGH. The GS1503 will check the parity (bit 8) for the CLK, CH1-4 and ECC0-5 words in the embedded audio data packets. When a parity bit error is detected in audio data packets ...
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... Host Interface setting for the corresponding audio group DID. When CASCADE is set LOW (external pin or register), the GS1503 will default to audio groups 1 and 2, where AOUT1/ 2 and AOUT3/4 will be demultiplexed from audio data packets with group 1 DID, and AOUT5/6 and AOUT7/8 will be demultiplexed from audio data packets with group 2 DID ...
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... CTRIDB[1:0] bits external pin or CASCADE bit 7 of Host Interface register 014h is set HIGH. When set HIGH, the GS1503 will default to audio groups 3 and 4. When set LOW, the GS1503 will default to audio groups 1 and 2. GS1503 ...
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... ACPG1_DET Audio group 1 control packet detection (1: Detection) When CASCADE is set LOW (external pin or register), the GS1503 will default to audio groups 1 and 2, where audio control packet data for channels will be demultiplexed from packets with group 1 DID, and audio control packet data for channels will be demultiplexed from packets with group 2 DID ...
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Register Settings NAME CTRONB Ch5-8 Audio control packet demultiplex enable (1: Enabled) CTRIDB[1:0] Ch5-8 Audio control packet DID set AF_NOB[8:0] Ch5-8 Audio frame number RATEB[2:0] Ch5-8 Sampling frequency data ASXB Ch5-8 Synchronization (0: Synchronous; 1: Non-synchronous) DEL1-2B[26:0] Ch5/6 Delay data ...
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... Arbitrary Data Demultiplexing in External Pin Mode This is the default mode for demultiplexing arbitrary data packets. The GS1503 will set the PKTEN external pin HIGH before arbitrary data will be output. Two VCLK cycles after PKTEN goes HIGH, arbitrary data is output on the PKT[7:0] bus ...
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... Field 2 multiplexing line ARBITUDW Arbitrary packet UDW 2.10 ANCILLARY DATA DELETION The GS1503 can be configured to delete the embedded ancillary data packets, after demultiplexing. There are two modes for ancillary data deletion. 2.10.1 Entire Ancillary Data Deletion When the ANCI external pin or ANCI bit 1 of Host Interface ...
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... GS1503 will be unable to reproduce the 48kHz audio word clock (fs) at the WCOUTA and WCOUTB pins in serial audio output modes. If the GS1503 used in conjunction with a HD audio module, which encodes audio clock phase information incorrectly, the DEC_MODE external pin or DECMODE bit 2 of Host Interface register 01Eh must be set HIGH ...
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... WCINA Fig. 43 Demultiplex Mode with 48kHz Word Clock Input System Example Figure 44 shows the timing relationship between the audio word clock inputs and word clock outputs when the GS1503 is configured to serial audio output mode. 1 CLK ACLKA/B WCINA/B WCOUTA/B Fig. 44 WCINA/B Input to WCOUTA/B Output Timing Diagram ...
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... HIGH. EXT_SEL External EXTH/EXTF input select. When set LOW, the EXTH and EXTF pins are configured as outputs. When set HIGH, the GS1503 will insert TRS and Line Numbers based on signals input at the EXTH and EXTF pins. SCRBYPASS Scramble processing bypass select. ...
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... See Section 2-12. MUXERRA Ch1-4 audio sample clock error. When set HIGH, the GS1503 is unable to recover the audio clock phase data in the embedded audio data packet for audio channels See Section 2-12. Audio AUDIO_CS[7:0] Audio Channel Status. When " ...
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... Valid only when "CS_MODE" is set HIGH. CS_RQST Audio Channel Status request. When set HIGH, the GS1503 will read and store the Audio Channel Status information from the audio channel set in Host Interface register "CH_SEL[2:0]". Valid only when "CS_MODE" is set HIGH. ...
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... GS1503 will perform error correction on audio data packets for channels based on the six ECC words. ECCA_ON Ch1-4 error correction enable. When set HIGH, the GS1503 will perform error correction on audio data packets for channels based on the six ECC words. DESCRIPTION ADDRESS ...
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... CASCADE Cascade select. When set HIGH, the GS1503 will default to audio groups 3 and 4. When set LOW, the GS1503 will default to audio groups 1 and 2. NOTE: The status of the CASCADE external pin is not updated in this register. The value programmed in this register is logical OR'd with the CASCADE external pin setting ...
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Table 14: Demultiplex Mode Host Interface Registers (Continued) CONTROL NAME ITEM DBNB_ERR Ch5-8 audio data packet DBN error. When set HIGH, a Data Block Number has been detected in the audio data packet for audio channels ADPB8B_ERR ...
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Table 14: Demultiplex Mode Host Interface Registers (Continued) CONTROL NAME ITEM Audio ACPG4_DET Audio group 4 control packet detect. When set Control HIGH, audio control packets with group 4 DID have Packet been detected in the incoming Luma video data ...
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Table 14: Demultiplex Mode Host Interface Registers (Continued) CONTROL NAME ITEM RSV Not used. CTRONA Ch1-4 audio control packet demultiplex enable. When set HIGH, the audio control packets in the Luma channel of the video data stream for audio channels ...
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Table 14: Demultiplex Mode Host Interface Registers (Continued) CONTROL NAME ITEM ADPG4_DEL Audio group 4 data packet delete. When set HIGH, all audio data packets with group 4 DID will be deleted from the Chroma video data stream. Valid only ...
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Table 14: Demultiplex Mode Host Interface Registers (Continued) CONTROL NAME ITEM Arbitrary ARBITON Arbitrary data packet demultiplex. Valid only when Data "ARBITMODE" is HIGH. When set HIGH, arbitrary data packets will be demultiplexed from the Luma Packet video data stream. ...
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REFERENCE DESIGN 3. REFERENCE DESIGN 3. REFERENCE DESIGN 3. REFERENCE DESIGN 3.1 CIRCUIT SCHEMATICS 3.1 CIRCUIT SCHEMATICS 3.1 CIRCUIT SCHEMATICS 3.1 CIRCUIT SCHEMATICS ...
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LFA_VCC 72 LFA 73 LBCONT 74 LFA_VEE 75 DFT_VEE LFS ...
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VCC GND VCC GND 15879 - 1 ...
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VCTR GND GND VCC O VCO 74 VCO 75 PD_VEE 76 PDSUB_VEE 77 IJI 78 ...
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J9 1 VCC R67 3 470R C87 C88 4 4 100uF/6.3V 100n LP 5.00/4/ PWR U10 LM1085_M EMF5 BLM31P330S G VCC C89 C90 100uF/6.3V 100n +3.3V R68 300R C91 C92 100uF/6.3V 100n D8 3.3V ...
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BOARD LAYOUTS 3.2 BOARD LAYOUTS 3.2 BOARD LAYOUTS 3.2 BOARD LAYOUTS 75 15879 - 1 ...
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76 15879 - 1 ...
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77 15879 - 1 ...
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78 15879 - 1 ...
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... R1,R3,R6,R8,R70,R72,R75, R77 27 4 R2,R7,R71,R76 28 6 R4,R9,R41,R42,R74,R78 29 4 R5,R10,R73,R79 30 4 R11,R12,R13,R14 31 2 R21,R15 PART 220n 100n 10n 680p * 1u 10u 0.5p 4u7 1.5p 47p 100uF/6.3V PG1101W DSS310-55D-223S BLM11A601S BLM31P330SG GS1503 74FCT74 CDC2510C TLC2272 CONN 24X2 BNC_BCJ_RPC_01 LP 5.00/4/90 12n 2N3904/TO 55R 191R 75R 100R 1k 100k 79 15879 - 1 ...
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BILL OF MATERIALS BILL OF MATERIALS (Continued) BILL OF MATERIALS BILL OF MATERIALS (Continued) (Continued) (Continued) ITEM QUANTITY REFERENCE 32 12 R16,R19,R22,R25,R26,R27, R28,R29,R30,R31,R32,R33 33 2 R17,R23 34 2 R24,R18 35 3 R34,R64,R65 36 8 R35,R36,R37,R49,R50,R52,R58, R59 ...
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REFERENCES & BIBLIOGRAPHY 4. REFERENCES & BIBLIOGRAPHY 4. REFERENCES & BIBLIOGRAPHY 4. REFERENCES & BIBLIOGRAPHY SMPTE 260M-1999 1125/60 High-Definition Production System - Digital Representation and Bit-Parallel Interface SMPTE 274M-1998 1920 x 1080 Scanning and Analog and Parallel Digital Interfaces ...
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... P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement 12˚ NOM 22 ± ...