LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 6

• Manufacturer Part Number: LM3S2965-IRN50-A1T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Table of Contents
13.5
14
14.1
14.2
14.2.1 Bit Rate Generation ................................................................................................................. 339
14.2.2 FIFO Operation ....................................................................................................................... 339
14.2.3 Interrupts ................................................................................................................................ 339
14.2.4 Frame Formats ....................................................................................................................... 340
14.3
14.4
14.5
15
15.1
15.2
15.2.1 I
15.2.2 Available Speed Modes ........................................................................................................... 378
15.2.3 Interrupts ................................................................................................................................ 379
15.2.4 Loopback Operation ................................................................................................................ 379
15.2.5 Command Sequence Flow Charts ............................................................................................ 380
15.3
15.4
15.5
15.6
16
16.1
16.2
16.3
16.4
16.4.1 Initialization ............................................................................................................................. 412
16.4.2 Operation ............................................................................................................................... 413
16.4.3 Transmitting Message Objects ................................................................................................. 413
16.4.4 Configuring a Transmit Message Object .................................................................................... 413
16.4.5 Updating a Transmit Message Object ....................................................................................... 414
16.4.6 Accepting Received Message Objects ...................................................................................... 414
16.4.7 Receiving a Data Frame .......................................................................................................... 415
16.4.8 Receiving a Remote Frame ...................................................................................................... 415
16.4.9 Receive/Transmit Priority ......................................................................................................... 415
16.4.10 Configuring a Receive Message Object .................................................................................... 415
16.4.11 Handling of Received Message Objects .................................................................................... 416
16.4.12 Handling of Interrupts .............................................................................................................. 416
16.4.13 Bit Timing Configuration Error Considerations ........................................................................... 417
16.4.14 Bit Time and Bit Rate ............................................................................................................... 417
16.4.15 Calculating the Bit Timing Parameters ...................................................................................... 419
16.5
16.6
17
17.1
6
Register Descriptions .............................................................................................................. 304
Synchronous Serial Interface (SSI) ................................................................................ 338
Block Diagram ........................................................................................................................ 338
Functional Description ............................................................................................................. 338
Initialization and Configuration ................................................................................................. 347
Register Map .......................................................................................................................... 348
Register Descriptions .............................................................................................................. 349
Inter-Integrated Circuit (I
Block Diagram ........................................................................................................................ 375
Functional Description ............................................................................................................. 375
Initialization and Configuration ................................................................................................. 386
I
Register Descriptions (I
Register Descriptions (I2C Slave) ............................................................................................. 401
Controller Area Network (CAN) Module ......................................................................... 410
Controller Area Network Overview ............................................................................................ 410
Controller Area Network Features ............................................................................................ 410
Controller Area Network Block Diagram .................................................................................... 411
Controller Area Network Functional Description ......................................................................... 412
Controller Area Network Register Map ...................................................................................... 421
Register Descriptions .............................................................................................................. 423
Analog Comparators ....................................................................................................... 451
Block Diagram ........................................................................................................................ 452
2
2
C Bus Functional Overview .................................................................................................... 376
C Register Map ..................................................................................................................... 387
2
C Master) ........................................................................................... 388
2
C) Interface ............................................................................ 375
Preliminary
November 30, 2007