LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 24

• Manufacturer Part Number: LM3S2965-IRN50-A1T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Architectural Overview
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Internal Memory
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General-Purpose Timers
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System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
Thumb®-compatible Thumb-2-only instruction set processor core for high code density
50-MHz operation
Hardware-division and single-cycle-multiplication
Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
42 interrupts with eight priority levels
Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
Unaligned data access, enabling data to be efficiently packed into memory
Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
256 KB single-cycle flash
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64 KB single-cycle SRAM
Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
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32-bit Timer modes
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User-managed flash block protection on a 2-KB block basis
User-managed flash data programming
User-defined and managed flash-protection block
As a single 32-bit timer
As one 32-bit Real-Time Clock (RTC) to event capture
For Pulse Width Modulation (PWM)
To trigger analog-to-digital conversions
Programmable one-shot timer
Programmable periodic timer
Real-Time Clock when using an external 32.768-KHz clock as the input
Preliminary
November 30, 2007