LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 154
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LM3S2965-IRN50-A1T
Manufacturer Part Number
LM3S2965-IRN50-A1T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IRN50-A1T.pdf
(574 pages)
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Internal Memory
Flash Memory Protection Program Enable 0 (FMPPE0)
Base 0x400F.D000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
154
Reset
Reset
Type
Type
Bit/Field
31:0
R/W
R/W
31
15
1
1
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset
0x134 and 0x400
Note:
Note:
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
R/W
R/W
30
14
PROG_ENABLE
1
1
Name
This register is aliased for backwards compatability.
Offset is relative to System Control base address of 0x400FE000.
R/W
R/W
29
13
1
1
R/W
R/W
28
12
1
1
R/W
R/W
Type
27
11
R/W
1
1
R/W
R/W
26
10
0xFFFFFFFF
1
1
Reset
R/W
R/W
25
1
9
1
Preliminary
PROG_ENABLE
PROG_ENABLE
Description
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
R/W
R/W
Value
0xFFFFFFFF
24
1
8
1
R/W
R/W
23
1
7
1
Description
Enables 256 KB of flash.
R/W
R/W
22
1
6
1
R/W
R/W
21
1
5
1
R/W
R/W
20
1
4
1
R/W
R/W
19
1
3
1
November 30, 2007
R/W
R/W
18
1
2
1
R/W
R/W
17
1
1
1
R/W
R/W
16
1
0
1
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