LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 10

• Manufacturer Part Number: LM3S2965-IRN50-A1T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Table of Contents
Figure 15-10. Master Burst RECEIVE .................................................................................................. 383
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 384
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 385
Figure 15-13. Slave Command Sequence ............................................................................................ 386
Figure 16-1.
Figure 16-2.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 18-1.
Figure 18-2.
Figure 18-3.
Figure 18-4.
Figure 18-5.
Figure 19-1.
Figure 19-2.
Figure 20-1.
Figure 23-1.
Figure 23-2.
Figure 23-3.
Figure 23-4.
Figure 23-5.
Figure 23-6.
Figure 23-7.
Figure 23-8.
Figure 23-9.
Figure 23-10. External Reset Timing (RST) .......................................................................................... 544
Figure 23-11. Power-On Reset Timing ................................................................................................. 545
Figure 23-12. Brown-Out Reset Timing ................................................................................................ 545
Figure 23-13. Software Reset Timing ................................................................................................... 545
Figure 23-14. Watchdog Reset Timing ................................................................................................. 545
Figure 24-1.
10
CAN Module Block Diagram ........................................................................................... 411
CAN Bit Time ................................................................................................................ 418
Analog Comparator Module Block Diagram ..................................................................... 452
Structure of Comparator Unit .......................................................................................... 453
Comparator Internal Reference Structure ........................................................................ 454
PWM Module Block Diagram .......................................................................................... 464
PWM Count-Down Mode ................................................................................................ 465
PWM Count-Up/Down Mode .......................................................................................... 466
PWM Generation Example In Count-Up/Down Mode ....................................................... 466
PWM Dead-Band Generator ........................................................................................... 467
QEI Block Diagram ........................................................................................................ 501
Quadrature Encoder and Velocity Predivider Operation .................................................... 502
Pin Connection Diagram ................................................................................................ 517
Load Conditions ............................................................................................................ 537
I
Hibernation Module Timing ............................................................................................. 540
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 541
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 541
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 542
JTAG Test Clock Input Timing ......................................................................................... 543
JTAG Test Access Port (TAP) Timing .............................................................................. 543
JTAG TRST Timing ........................................................................................................ 543
100-Pin LQFP Package .................................................................................................. 546
2
C Timing ..................................................................................................................... 540
Preliminary
November 30, 2007