LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 565
![no-image](/images/no-image-200.jpg)
LM3S2965-IRN50-A1T
Manufacturer Part Number
LM3S2965-IRN50-A1T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IRN50-A1T.pdf
(574 pages)
- Current page: 565 of 574
- Download datasheet (6Mb)
November 30, 2007
SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
Inter-Integrated Circuit (I
I
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
I2CMSA, type R/W, offset 0x000, reset 0x0000.0000
I2CMCS, type RO, offset 0x004, reset 0x0000.0000
I2CMCS, type WO, offset 0x004, reset 0x0000.0000
I2CMDR, type R/W, offset 0x008, reset 0x0000.0000
I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001
I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000
I2CMRIS, type RO, offset 0x014, reset 0x0000.0000
I2CMMIS, type RO, offset 0x018, reset 0x0000.0000
I2CMICR, type WO, offset 0x01C, reset 0x0000.0000
2
C Master
31
15
30
14
29
13
2
C) Interface
28
12
27
11
26
10
25
9
Preliminary
24
8
23
7
BUSBSY
22
6
IDLE
21
5
ARBLST
SA
20
4
DATA
PID1
PID2
PID3
CID0
CID1
CID2
CID3
TPR
DATACK
ACK
LM3S2965 Microcontroller
19
3
ADRACK
STOP
18
2
ERROR
START
17
1
BUSY
RUN
MIS
R/S
RIS
16
IM
IC
0
565
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