LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 543

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LM3S2965-IRN50-A1T

Manufacturer Part Number
LM3S2965-IRN50-A1T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
23.2.9
November 30, 2007
Figure 23-7. JTAG Test Clock Input Timing
Figure 23-8. JTAG Test Access Port (TAP) Timing
Figure 23-9. JTAG TRST Timing
General-Purpose I/O
Note:
Parameter No.
t
TCK
TDO_DVZ
TMS
TDO
TCK
J13
J14
J15
TDI
All GPIOs are 5 V-tolerant.
TRST
TCK
TCK fall to High-Z from Data Valid
J11
J6
Parameter
t
TRST_SU
t
TRST
TDI Input Valid
J9
TMS Input Valid
J7
TDO Output Valid
J10
Preliminary
J14
J8
J3
Parameter Name
8-mA drive with slew rate control
TRST assertion time
TRST setup time to TCK rise
J5
J12
J2
2-mA drive
4-mA drive
8-mA drive
J15
TDI Input Valid
J9
TMS Input Valid
J7
J4
TDO Output Valid
J10
J8
Min
100
10
LM3S2965 Microcontroller
-
Nom
9
7
6
7
-
-
Max
11
9
8
9
-
-
J13
Unit
ns
ns
ns
ns
ns
ns
543

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