ST7FL15F1MAE STMICROELECTRONICS [STMicroelectronics], ST7FL15F1MAE Datasheet - Page 62

• Manufacturer Part Number: ST7FL15F1MAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, data EEPROM, ADC, 5 timers, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7L15, ST7L19
DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d)
11.2.3.6 One Pulse Mode (available only on
Flash devices)
One Pulse mode can be used to control PWM2/3
signal with an external LTIC pin. This mode is
available only in dual timer mode that is only for
CNTR2, when the OP_EN bit in PWM3CSR regis-
ter is set.
One Pulse mode is activated by the external LTIC
input. The active edge of the LTIC pin is selected
by the OPEDGE bit in the PWM3CSR register.
After obtaining the active edge of the LTIC pin,
CNTR2 is reset (000h) and PWM3 is set to high.
CNTR2 starts counting from 000h and when it
reaches the active DCR3 value, PWM3 goes low.
Until this time, any further transitions on the LTIC
signal will have no effect. If there are LTIC transi-
tions after CNTR2 reaches the DCR3 value,
CNTR2 is reset again and PWM3 goes high.
If there are no more LTIC active edges after the
first active edge, CNTR2 counts until it reaches the
ARR2 value, it is then reset and PWM3 is set to
high. The counter again starts counting from 000h.
When it reaches the active DCR3 value, PWM3
goes low, after which the counter counts until it
reaches ARR2, it is reset and PWM3 is set to high
again, and the cycle continues in this manner.
The same operation applies for PWM2, but in this
case the comparison is done on DCR2
OP_EN and OPEDGE bits take effect on the fly
and are not synchronized with the Counter 2 over-
flow.
The output bit OP2/3 can be used to invert the po-
larity of PWM2/3 in One Pulse mode. The update
of these bits (OP2/3) is synchronized with the
Counter 2 overflow, provided the TRAN2 bit is set.
Notes:
1. The time taken from activation of LTIC input and
CNTR2 reset is between 1 and 2 t
is 125n to 250ns (with 8 MHz f
2. To avoid spurious interrupts, the LiteTimer input
capture interrupt should be disabled while 12-bit
ARTimer is in One Pulse mode.
3. Priority of various conditions is as follows for
PWM3:
Break > One Pulse mode with active LTIC edge >
Forced overflow by s/w > One Pulse mode without
active LTIC edge > normal PWM operation.
4. It is possible to update DCR2/3 and OP2/3 at
the Counter 2 reset because the update is syn-
chronized with the counter reset. This is managed
by the overflow interrupt which is generated if the
62/138
1
CPU
CPU
).
cycles, that
counter is reset either due to ARR match or active
pulse at LTIC pin.
5. DCR2/3 and OP2/3 update in One Pulse mode
is done dynamically using force update in soft-
ware.
6. DCR3 update in this mode is not synchronized
with any event. That may lead to a longer next
PWM3 cycle duration than expected just after the
change (refer to
7. In One Pulse mode, the ATR2 value must be
greater than the DCR2/3 value for PWM2/3 (oppo-
site to normal PWM mode).
8. If there is an active edge on the LTIC pin after
the counter has reset due to an ARR2 match, then
the timer again is reset and appears as modified
Duty cycle, depending on whether the new DCR
value is less than or more than the previous value.
9. The TRAN2 bit should be set along with the
FORCE2 bit with the same instruction after a write
to the DCR register.
10. ARR2 value should be changed after an over-
flow in One Pulse mode to avoid any irregular
PWM cycle.
11. When exiting from One Pulse mode, the
OP_EN bit in the PWM3CSR register should be
reset first and then the ENCNTR2 bit (if Counter 2
must be stopped).
How to enter One Pulse mode:
1. Load ATR2H/ATR2L with required value.
2. Load DCR3H/DCR3L for PWM3. ATR2 value
must be greater than DCR3.
3. Set OP3 in PWM3CSR if polarity change is re-
quired.
4. Select CNTR2 by setting ENCNTR2 bit in
ATCSR2.
5. Set TRAN2 bit in ATCSR2 to enable transfer.
6. "Wait for Overflow" by checking the OVF2 flag in
ATCSR2.
7. Select counter clock using CK<1:0> bits in ATC-
SR.
8. Set OP_EN bit in PWM3CSR to enable One
Pulse mode.
9. Enable PWM3 by OE3 bit of PWMCR.
The "Wait for Overflow" in step 6 can be replaced
by forced update.
Follow the same procedure for PWM2 with the bits
corresponding to PWM2.
Note: When break is applied in One Pulse mode,
DUAL 12-BIT AUTORELOAD TIMER 4, CNTR2,
DCR2/3 and ATR2 registers are reset. Conse-
Figure
46).