ST7FL15F1MAE STMICROELECTRONICS [STMicroelectronics], ST7FL15F1MAE Datasheet
ST7FL15F1MAE
Related parts for ST7FL15F1MAE
ST7FL15F1MAE Summary of contents
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MCU for automotive with single voltage Flash/ROM memory, Features Memories ■ – 4 Kbytes single voltage extended Flash (XFlash) or ROM with readout protection, In- Circuit programming and In-Application Pro- gramming (ICP and IAP), 10K write/erase cy- cles guaranteed, ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST7L15, ST7L19 1 INTRODUCTION 1.1 DESCRIPTION The ST7L1x is a member of the ST7 microcontrol- ler family suitable for automotive applications. All ST7 devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set. The ...
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PIN DESCRIPTION Figure 2. 20-Pin SO Package Pinout SS/AIN0/PB0 SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 CLKIN/AIN4/PB4 AIN5/PB5 AIN6/PB6 Notes: 1. This pin cannot be configured as external interrupt in ROM devices. 2. OSC1 and OSC2 are not multiplexed in ROM devices and ...
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ST7L15, ST7L19 Pin No. Pin Name SO20 4 PB0/AIN0/SS I/O 5 PB1/AIN1/SCK I/O 6 PB2/AIN2/MISO I/O 7 PB3/AIN3/MOSI I/O PB4/AIN4/CLKIN I/O COMPIN PB5/AIN5 I PB6/AIN6 I PA7 I/O C PA6 /MCO/ 12 ...
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REGISTER AND MEMORY MAP As shown in Figure 3, the MCU can address 64 Kbytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 256 bytes of RAM, 128 bytes of data ...
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ST7L15, ST7L19 REGISTER AND MEMORY MAP (cont’d) Table 2. Hardware Register Map Address Block Register Label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h PBDR 0004h Port B PBDDR 0005h PBOR 0006h PCDR Port C 0007h PCDDR 0008h LTCSR2 ...
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Address Block Register Label 0031h SPIDR 0032h SPI SPICR 0033h SPICSR 0034h ADCCSR 0035h ADC ADCDRH 0036h ADCDRL 0037h ITC EICR 0038h MCC MCCSR 0039h Clock and RCCR 003Ah Reset SICSR PLL clock 003Bh PLLTST select 003Ch ITC EISR 003Dh ...
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ST7L15, ST7L19 4 FLASH PROGRAM MEMORY 4.1 INTRODUCTION The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The XFlash ...
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FLASH PROGRAM MEMORY (cont’d) 4.4 ICC INTERFACE ICP needs a minimum of four and up to six pins to be connected to the programming tool. These pins are: – RESET: Device reset – Device power supply ground SS ...
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ST7L15, ST7L19 FLASH PROGRAM MEMORY (cont’d) 4.5 MEMORY PROTECTION There are two different types of memory protec- tion: Readout Protection and Write/Erase Protec- tion, which can be applied individually. 4.5.1 Readout Protection Readout protection, when selected, protects against program memory ...
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DATA EEPROM 5.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non volatile back- up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. Figure 5. EEPROM Block ...
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ST7L15, ST7L19 DATA EEPROM (cont’d) 5.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEP- ROM Control/Status register (EECSR). The flow- chart in Figure 6 describes these different memory access modes. ...
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DATA EEPROM (cont’d) Figure 7. Data EEPROM Write Operation ⇓ Row / Byte ⇒ ROW DEFINITION Byte 1 Byte 2 Writing data latches E2LAT bit Set by USER application E2PGM bit Note programming cycle is interrupted (by a ...
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ST7L15, ST7L19 DATA EEPROM (cont’d) 5.4 POWER SAVING MODES Wait mode The data EEPROM can enter WAIT mode on exe- cution of the WFI instruction of the microcontroller or when the microcontroller enters ACTIVE HALT mode.The data EEPROM immediately enters ...
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DATA EEPROM (cont’d) 5.7 REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EEC- SR) Read/Write Reset Value: 0000 0000 (00h Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This ...
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ST7L15, ST7L19 6 CENTRAL PROCESSING UNIT 6.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 MAIN FEATURES 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 main ...
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CPU REGISTERS (cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This ...
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ST7L15, ST7L19 CPU REGISTERS (cont’d) STACK POINTER (SP) Read/Write Reset Value: 01FFh SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which always points to the next free location in ...
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SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example, in case of a power brown-out) and re- ducing the number of external components. Main features Clock ...
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ST7L15, ST7L19 SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d) 7.2 PHASE LOCKED LOOP The PLL can be used to multiply a 1 MHz frequen- cy from the RC oscillator or the external clock obtain f of ...
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SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d) Figure 12. Clock Management Block Diagram 7 CR9 CR8 CR7 Tunable 1% RC OSC,PLLOFF, CLKSEL[1:0] Option bits CLKIN CLKIN CLKIN CLKIN OSC /OSC1 1-16 MHz OSC2 f OSC /32 DIVIDER 7 PLLDIV2 0 CR6 ...
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ST7L15, ST7L19 SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d) 7.4 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multi- oscillator block ( MHz): An external source ■ Crystal ...
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SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d) 7.5 RESET SEQUENCE MANAGER (RSM) 7.5.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG ...
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ST7L15, ST7L19 Figure 14. Reset Block Diagram RESET Note 1: See “Illegal Opcode Reset” on page 95 26/138 Filter PULSE GENERATOR for more details on illegal opcode reset conditions. INTERNAL RESET WATCHDOG RESET 1) ILLEGAL ...
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SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance noisy environment recommended to follow the guidelines mentioned in Section 13 ELECTRICAL CHARACTERISTICS. 7.5.3 External ...
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ST7L15, ST7L19 SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d) 7.6 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low Voltage Detector (LVD) function managed by the SICSR register. Note: A reset can also be triggered following ...
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SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d) Figure 17. Reset and Supply Management Block Diagram RESET SEQUENCE RESET 7.6.2 Low-Power Modes Mode Description WAIT No effect on SI. HALT The SICSR register is frozen. WATCHDOG TIMER (WDG) ...
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ST7L15, ST7L19 SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d) 7.6.3 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 0110 0xx0 (6xh) 7 WDG Res CR1 CR0 LOCKED RF Bit 7 = Reserved (should be 0) Bits 6:5 = ...
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INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: Maskable hardware interrupts as listed in Table 5, “Interrupt Mapping,” on page 32 and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart is shown ...
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ST7L15, ST7L19 INTERRUPTS (cont’d) Figure 18. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION Table 5. Interrupt Mapping Source No. Block RESET Reset TRAP Software Interrupt 0 AWU Auto Wake-Up Interrupt 1 ei0 External Interrupt 0 2 ei1 External Interrupt 1 ...
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INTERRUPTS (cont’d) EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS31 IS30 IS21 IS20 IS11 Bits 7:6 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei3 (Port B0) according to Table Bits 5:4 ...
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ST7L15, ST7L19 INTERRUPTS (cont’d) Bits 3:2 = ei1[1:0] ei1 pin selection These bits are written by software. They select the Port A I/O pin used for the ei1 external interrupt ac- cording to the table below. External Interrupt I/O pin ...
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POWER SAVING MODES 9.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, five main pow- er saving modes are implemented in the ST7 (see Figure 19): Slow ■ Wait (and ...
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ST7L15, ST7L19 POWER SAVING MODES (cont’d) 9.3 WAIT MODE WAIT mode places the MCU into a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. ...
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POWER SAVING MODES (cont’d) 9.4 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when ACTIVE HALT is disabled (see section 9.5 on page 38 when the ...
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ST7L15, ST7L19 POWER SAVING MODES (cont’d) 9.4.1 Halt Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from HALT mode. – When using an external interrupt to wake up the microcontroller, re-initialize the ...
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POWER SAVING MODES (cont’d) Figure 25. ACTIVE HALT Mode Flowchart OSCILLATOR HALT INSTRUCTION PERIPHERALS (Active Halt enabled) CPU (AWUCSR.AWUEN=0) I BIT INTERRUPT Y OSCILLATOR PERIPHERALS CPU I BIT 256 OR 4096 CPU CLOCK OSCILLATOR PERIPHERALS CPU I ...
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ST7L15, ST7L19 POWER SAVING MODES (cont’d) Similarities with Halt mode The following AWUFH mode behavior is the same as normal HALT mode: – The MCU can exit AWUFH mode by means of any interrupt with exit from Halt capability or ...
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POWER SAVING MODES (cont’d) Figure 28. AWUFH Mode Flowchart HALT INSTRUCTION (Active Halt disabled) (AWUCSR.AWUEN=1) ENABLE 0 1) WDGHALT 1 AWU RC OSC WATCHDOG MAIN OSC RESET PERIPHERALS CPU I[1:0] BITS INTERRUPT AWU RC OSC Y MAIN ...
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ST7L15, ST7L19 POWER SAVING MODES (cont’d) 9.6.0.1 Register Description AWUFH CONTROL/STATUS REGISTER (AWUCSR) Read/Write Reset Value: 0000 0000 (00h Bits 7:3 = Reserved. Bit 1 = AWUF Auto Wake-Up Flag This bit is set ...
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I/O PORTS 10.1 INTRODUCTION The I/O ports allow data transfer. An I/O port con- tains up to eight pins. Each pin can be pro- grammed independently either as a digital input or digital output. In addition, specific pins may ...
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ST7L15, ST7L19 I/O PORTS (cont’d) – Set the interrupt mask with the SIM instruction SIM (in cases where a pin level change could occur) – Select falling edge – Disable the external interrupt through the OR register – Select rising ...
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I/O PORTS (cont’d) Figure 29. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS From on-chip periphera ALTERNATE ENABLE BIT DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT REQUEST ( SENSITIVITY ...
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ST7L15, ST7L19 I/O PORTS (cont’d) Table 9. I/O Configurations PAD PAD PAD Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register reads the alternate function ...
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I/O PORTS (cont’d) Analog alternate function Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected ...
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ST7L15, ST7L19 I/O PORTS (cont’d) 10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION The I/O port register configurations are summa- rized as follows: Standard Ports PA7:0, PB6:0 MODE floating input pull-up input open drain output push-pull output PC1:0 (multiplexed with OSC1,OSC2) MODE floating ...
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Address Register (Hex.) Label PAOR MSB 0002h Reset Value PBDR MSB 0003h Reset Value PBDDR MSB 0004h Reset Value PBOR MSB 0005h Reset Value PCDR MSB 0006h Reset Value PCDDR MSB 0007h Reset Value 10.8 MULTIPLEXED INPUT/OUTPUT PORTS OSC1/PC0 are ...
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ST7L15, ST7L19 11 ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the ...
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ON-CHIP PERIPHERALS (cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. This downcounter is free- running: It counts down, even if the watchdog is disabled. The value ...
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ST7L15, ST7L19 11.2 DUAL 12-BIT AUTORELOAD TIMER 4 (AT4) 11.2.1 Introduction The 12-bit Autoreload Timer can be used for gen- eral-purpose timing functions based on one or two free-running 12-bit upcounters with an input capture register and four ...
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DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) Figure 33. Dual Timer Mode (ENCNTR2 = 1) ATIC Edge Detection Circuit 12-bit Autoreload Register 1 12-bit Upcounter 1 12-bit Upcounter 2 12-bit Autoreload Register 2 Clock Control LTIC 12-bit Input Capture PWM0 Duty ...
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ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) 11.2.3 Functional Description 11.2.3.1 PWM Mode This mode allows up to four Pulse Width Modulat- ed signals to be generated on the PWMx output pins. PWM Frequency The four PWM signals can ...
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DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) Figure 35. PWM Function 4095 DUTY CYCLE REGISTER (DCRx) AUTO-RELOAD REGISTER (ATR) 000 WITH OE=1 AND OPx=0 WITH OE=1 AND OPx=1 Figure 36. PWM Signal from 0% to 100% Duty Cycle f COUNTER COUNTER ...
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ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) 11.2.3.2 Dead Time Generation A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is required for half-bridge driving where PWM signals must not be overlapped. The ...
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DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) 11.2.3.3 Break Function The break function can be used to perform an emergency shutdown of the application being driv the PWM signals. The break function is activated by the external BREAK pin. ...
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ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) 11.2.3.4 Output Compare Mode To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers. When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH ...
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DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) 11.2.3.5 Input Capture Mode The 12-bit ATICR register is used to latch the val the 12-bit free running upcounter CNTR1 af- ter a rising or falling edge is detected on the ATIC ...
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ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) Long Input Capture ■ Pulses that last more than 8µs can be measured with an accuracy of 4µ OSC following conditions: – The 12-bit AT4 Timer is clocked by the ...
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DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) – At the second input capture on the falling edge of the pulse, we assume that the values in the reg- isters are as follows: LTICR = LT2 ATICRH = ATH2 ATICRL = ATL2 ...
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ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) 11.2.3.6 One Pulse Mode (available only on Flash devices) One Pulse mode can be used to control PWM2/3 signal with an external LTIC pin. This mode is available only in dual timer ...
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DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) quently, these registers must be initialized again when break is removed. Figure 44. Block Diagram of One Pulse Mode LTIC pin Edge Selection OPEDGE PWM3CSR Register Figure 45. One Pulse Mode Timing Diagram f ...
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ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) 11.2.3.7 Force Update (available only on Flash devices) In order not to wait for the counter load the value into active DCRx registers, a pro- grammable counter overflow is provided. For x ...
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DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) 11.2.6 Register Description TIMER CONTROL STATUS REGISTER (ATCSR) Read / Write Reset Value: 0x00 0000 (x0h ICF ICIE CK1 CK0 Bit 7 = Reserved, must be kept cleared Bit 6 = ICF ...
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ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) AUTORELOAD REGISTER (ATR1H) Read / Write Reset Value: 0000 0000 (00h ATR11 ATR10 ATR9 AUTORELOAD REGISTER (ATR1L) Read / Write Reset Value: 0000 0000 (00h) 7 ATR7 ...
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DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) BREAK CONTROL REGISTER (BREAKCR) Read/Write Reset Value: 0000 0000 (00h BREDGE BA BPEN PWM3 PWM2 PWM1 PWM0 Bit 7 = Reserved, must be kept cleared Bit 6 = BREDGE Break Input Edge ...
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ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) Bits 11:0 = ICR[11:0] Input Capture Data This is a 12-bit register which is readable by soft- ware and cleared by hardware after a reset. The ATICR register contains the captured value ...
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DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) Bit 1 = TRAN2 Transfer Enable 2 This bit is read/write by software, cleared by hard- ware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR2. It ...
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ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d) Table 14. Register Map and Reset Values Address Register 7 (Hex.) Label ATCSR 0D 0 Reset Value CNTR1H 0E 0 Reset Value CNTR1L CNTR1_7 0F Reset Value 0 ATR1H 10 0 Reset ...
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Address Register 7 (Hex.) Label ATCSR2 FORCE2 21 Reset Value 0 BREAKCR BRSEL 22 Reset Value 0 ATR2H 23 0 Reset Value ATR2L ATR7 24 Reset Value 0 DTGR DTE 25 Reset Value 0 BREAKEN 26 0 Reset Value 6 ...
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ST7L15, ST7L19 11.3 LITE TIMER 2 (LT2) 11.3.1 Introduction The Lite Timer can be used for general-purpose timing functions based on two free-running 8- bit upcounters and an 8-bit input capture register. 11.3.2 Main Features Realtime Clock ■ ...
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LITE TIMER (cont’d) 11.3.3 Functional Description 11.3.3.1 Timebase Counter 1 The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from frequency of f overflow event occurs ...
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ST7L15, ST7L19 LITE TIMER (cont’d) 11.3.4 Low Power Modes Mode Description No effect on Lite timer SLOW (this peripheral is driven directly by f /32) OSC WAIT No effect on Lite timer ACTIVE HALT No effect on Lite timer HALT ...
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LITE TIMER (cont’d) Bit 6 = ICF Input Capture Flag This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value input capture 1: ...
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ST7L15, ST7L19 ON-CHIP PERIPHERALS (cont’d) 11.4 SERIAL PERIPHERAL INTERFACE (SPI) 11.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or ...
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SERIAL PERIPHERAL INTERFACE (SPI) (cont’d) Figure 50. Serial Peripheral Interface Block Diagram SPIDR MOSI MISO 8-bit Shift Register SOD bit SCK SS Data/Address Bus Read Read Buffer Write MASTER CONTROL SERIAL CLOCK GENERATOR ST7L15, ST7L19 Interrupt request 7 SPIF WCOL ...
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ST7L15, ST7L19 SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 51. The MOSI pins are connected together and the MISO pins are connected together. ...
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SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM ...
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ST7L15, ST7L19 SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). ...
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SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 54). Note: The idle state of SCK must correspond to the polarity selected ...
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ST7L15, ST7L19 SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.5 Error Flags 11.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master de- vice’s SS pin is pulled low. When a Master mode fault occurs: – The MODF bit is set ...
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SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.5.4 Single Master Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured using a device as the master and ...
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ST7L15, ST7L19 SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.6 Low Power Modes Mode Description No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI ...
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SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.8 Register Description SPI CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 Bit 7 = SPIE Serial Peripheral Interrupt Enable This bit is set and cleared by ...
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ST7L15, ST7L19 SERIAL PERIPHERAL INTERFACE (cont’d) SPI CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF - Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only) This bit is ...
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SERIAL PERIPHERAL INTERFACE (cont’d) Table 17. SPI Register Map and Reset Values Address Register (Hex.) Label SPIDR MSB 0031h Reset Value SPICR SPIE 0032h Reset Value SPICSR SPIF 0033h Reset Value SPE SPR2 MSTR ...
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ST7L15, ST7L19 ON-CHIP PERIPHERALS (cont’d) 11.5 10-BIT A/D CONVERTER (ADC) 11.5.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has up to seven ...
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A/D CONVERTER (ADC) (cont’d) 11.5.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input voltage ...
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ST7L15, ST7L19 10-BIT A/D CONVERTER (ADC) (cont’d) 11.5.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON 0 0 Bit 7 = EOC End of Conversion This bit is ...
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A/D CONVERTER (ADC) (cont’d) Table 18. ADC Register Map and Reset Values Address Register (Hex.) Label ADCCSR 0034h Reset Value ADCDRH 0035h Reset Value ADCDRL 0036h Reset Value EOC SPEED ADON ...
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ST7L15, ST7L19 12 INSTRUCTION SET 12.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in seven main groups: Addressing Mode Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld ...
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ST7 ADDRESSING MODES (cont’d) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For ...
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ST7L15, ST7L19 ST7 ADDRESSING MODES (cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an ...
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INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and ...
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ST7L15, ST7L19 INSTRUCTION GROUPS (cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true ...
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INSTRUCTION GROUPS (cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset carry ...
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ST7L15, ST7L19 13 ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 13.1.1 Minimum and Maximum Values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst con- ditions ...
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ELECTRICAL CHARACTERISTICS (cont’d) 13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 13.2.1 ...
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ST7L15, ST7L19 ELECTRICAL CHARACTERISTICS (cont’d) 13.3 OPERATING CONDITIONS 13.3.1 General Operating Conditions T = -40 to +125°C, unless otherwise specified. A Symbol Parameter V Supply voltage DD f External clock frequency on CLKIN pin CLKIN T Ambient temperature range A ...
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OPERATING CONDITIONS (cont’d) The RC oscillator and PLL characteristics are temperature-dependent. 13.3.1.1 Operating Conditions (tested for T Symbol Parameter 1) f Internal RC oscillator frequency RC Accuracy of Internal RC oscillator ACC RC with RCCR = RCCR0 I RC oscillator ...
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ST7L15, ST7L19 OPERATING CONDITIONS (cont’d) Figure 62 and Temperature for Calibrated RCCR0 RC DD 1.025 1.02 1.015 1.01 1.005 1 0.995 0.99 0.985 0.98 4.5 4.6 13.3.1.2 Operating Conditions (tested for T 1) Symbol Parameter Internal RC ...
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OPERATING CONDITIONS (cont’d) Figure 63. Typical Accuracy with RCCR = RCCR1 vs V 1.50% 1.00% 0.50% 0.00% -0.50% -1.00% Figure 64 and Temperature for Calibrated RCCR1 RC DD 1.01 1.005 1 0.995 0.99 0.985 0. ...
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ST7L15, ST7L19 OPERATING CONDITIONS (cont’d) Figure 65. PLLx4 Output vs CLKIN Frequency 7.00 6.00 5.00 4.00 3.00 2.00 1.00 1 1.5 External Input Clock Frequency (MHz) Note /2*PLL4 OSC CLKIN 104/138 Figure 66. PLLx8 Output vs CLKIN ...
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OPERATING CONDITONS (cont’d) 13.3.2 Operating Conditions with Low Voltage Detector (LVD -40 to +125°C, unless otherwise specified. A Symbol Parameter V Reset release threshold (V IT+ (LVD) V Reset generation threshold (V (LVD) IT- V LVD voltage threshold ...
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ST7L15, ST7L19 ELECTRICAL CHARACTERISTICS (cont’d) 13.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To obtain the total device consumption, ...
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SUPPLY CURRENT CHARACTERISTICS (cont’d) Figure 69. Typical I in SLOW 0.90 250KHz 0.80 0.70 125KHz 0.60 62KHz 0.50 0.40 0.30 0.20 0.10 0.00 2.7 3.3 VDD (V) Note: Graph displays data beyond the normal operating range of ...
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ST7L15, ST7L19 SUPPLY CURRENT CHARACTERISTICS (cont’d) 13.4.2 On-chip Peripherals Symbol Parameter I 12-bit Auto-Reload Timer supply current DD(AT SPI supply current DD(SPI) I ADC supply current when converting DD(ADC) Notes: 1. Data based on a differential I DD ...
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CLOCK AND TIMING CHARACTERISTICS (cont’d) 13.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with ten different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external ...
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ST7L15, ST7L19 ELECTRICAL CHARACTERISTICS (cont’d) 13.6 MEMORY CHARACTERISTICS 13.6.1 RAM and Hardware Registers T = -40 to +125°C, unless otherwise specified. A Symbol Parameter V Data retention mode RM 13.6.2 Flash Program Memory T = -40 to +85°C, unless otherwise ...
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ELECTRICAL CHARACTERISTICS (cont’d) 13.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 13.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling two LEDs through I/O ports), the ...
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ST7L15, ST7L19 EMC CHARACTERISTICS (cont’d) 13.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more ...
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ELECTRICAL CHARACTERISTICS (cont’d) 13.8 I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys I Input ...
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ST7L15, ST7L19 I/O PORT PIN CHARACTERISTICS (cont’d) 13.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when eight pins are sunk at same time (see Figure 77) ...
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I/O PORT PIN CHARACTERISTICS (cont’d) Figure 76. Typical 0.6 140°C 0.5 90°C 25°C 0.4 -5°C 0.3 -45°C 0.2 0 0.5 1 1.5 Iol (mA) Figure 77. Typical 140°C 1.2 90°C ...
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ST7L15, ST7L19 I/O PORT PIN CHARACTERISTICS (cont’d) Figure 82. Typical 0.6 0.5 0.4 0.3 0.2 0 2.5 3 3.5 4 VDD (V) Figure 83. Typical 0.7 0.6 0.5 0.4 0.3 ...
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I/O PORT PIN CHARACTERISTICS (cont’d) Figure 88. Typical 1.6 140°C 1.4 90°C 1.2 25°C 1 -5°C 0.8 -45°C 0.6 0.4 0 Iol (mA) Figure 89. Typical ...
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ST7L15, ST7L19 ELECTRICAL CHARACTERISTICS (cont’d) 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin T = -40 to +125°C, unless otherwise specified. A Symbol Parameter 1) V Input low-level voltage Input high-level voltage IH V Schmitt trigger voltage ...
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CONTROL PIN CHARACTERISTICS (cont’d) Figure 94. RESET Pin Protection When LVD Is Enabled Required EXTERNAL RESET 0.01µF Figure 95. RESET Pin Protection When LVD Is Disabled USER EXTERNAL RESET CIRCUIT 0.01µF Required Note 1: – The reset network protects the ...
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ST7L15, ST7L19 ELECTRICAL CHARACTERISTICS (cont’d) 13.10 COMMUNICATION INTERFACE CHARACTERISTICS 13.10.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter SCK SPI clock ...
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COMMUNICATION INTERFACE CHARACTERISTICS (cont’d) Figure 97. SPI Slave Timing Diagram with CPHA = 1 SS INPUT t su(SS) CPHA = 1 CPOL = 0 CPHA = 1 CPOL = 1 t w(SCKH) t a(SO) t w(SCKL) See MISO OUTPUT HZ ...
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ST7L15, ST7L19 ELECTRICAL CHARACTERISTICS (cont’d) 13.11 10-BIT ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Conversion voltage range AIN R External input resistor AIN C Internal sample and hold capacitor ADC ...
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ADC CHARACTERISTICS (cont’d) Table 21. ADC Accuracy with 3V < V Symbol Parameter |E | Total unadjusted error Offset error Gain error Differential linearity error Integral linearity ...
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ST7L15, ST7L19 14 PACKAGE CHARACTERISTICS In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level in- terconnect. The category of second level intercon- nect is marked on the package and ...
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PACKAGE CHARACTERISTICS (cont’d 14.2 SOLDERING INFORMATION In accordance with the RoHS European directive, all STMicroelectronics packages have been con- verted to lead-free technology, named ECO- PACK™. ECOPACK™ packages are qualified according ■ to the JEDEC STD-020C compliant soldering profile. Detailed ...
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ST7L15, ST7L19 15 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (Flash) as well as in factory coded versions (ROM). ST7L1x devices are ROM versions. ST7PL1x devices are Factory Advanced Service Technique ...
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OPTION BYTES (cont’d) 15.1.1 Flash Option Bytes The 2 option bytes allow the hardware configura- tion of the microcontroller to be selected. OPTION BYTE 0 OPT7 = Reserved (must be set to 0) OPT6 = Reserved (must be set to ...
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ST7L15, ST7L19 FLASH OPTION BYTES (cont’d) OPT 1 = WDGSW Hardware or Software Watch- dog 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) Table 25. List of Valid Option Combinations Operating conditions V range Clock ...
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OPTION BYTES (cont’d) 15.1.2 ROM Option Bytes The 2 option bytes allow the hardware configura- tion of the microcontroller to be selected. OPTION BYTE 0 OPT7 = AWUCK Auto Wake Up Clock Selection 0: 32 kHz oscillator (VLP) selected as ...
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... DEVICE CONFIGURATION AND ORDERING INFORMATION (cont’d) 15.2 DEVICE ORDERING INFORMATION Figure 102. Flash Commercial Product Code Structure DEVICE E2DATA PINOUT PROG MEM Table 26. Flash User Programmable Device Types Program Memory Part Number (bytes) ST7FL15F1MAE ST7FL19F1MAE 4K Flash ST7FL15F1MCE ST7FL19F1MCE 130/138 PACKAGE VERSION Leadfree (ECOPACK™ ...
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DEVICE CONFIGURATION AND ORDERING INFORMATION (cont’d) Figure 103. FASTROM Commercial Product Code Structure DEVICE E2DATA PINOUT PROG MEM Table 27. FASTROM Factory Coded Device Types Program Memory Part Number (bytes) ST7PL15F1MAE ST7PL19F1MAE 4K FASTROM ST7PL15F1MCE ST7PL19F1MCE PACKAGE VERSION XXX R ...
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ST7L15, ST7L19 DEVICE CONFIGURATION AND ORDERING INFORMATION (cont’d) Figure 104. ROM Commercial Product Code Structure DEVICE E2DATA PINOUT PROG MEM Table 28. ROM Factory Coded Device Types Program Memory Part Number (bytes) ST7L15F1MAE ST7L19F1MAE 4K ROM ST7L15F1MCE ST7L19F1MCE 132/138 PACKAGE ...
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ST7L1 FASTROM & ROM MICROCONTROLLER OPTION LIST Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST7L15, ST7L19 DEVICE CONFIGURATION AND ORDERING INFORMATION (cont’d) 15.3 DEVELOPMENT TOOLS Development tools for the ST7 microcontrollers in- clude a complete range of hardware systems and software tools from STMicroelectronics and third- party tool suppliers. The range of tools includes ...
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ST7 APPLICATION NOTES All relevant ST7 application notes can be found on www.st.com. ST7L15, ST7L19 135/138 ...
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ST7L15, ST7L19 16 REVISION HISTORY Table 30. Revision History Date Revision 16-Aug-2006 1 Initial release Replaced “ST7L1” with “ST7L15, ST7L19” in document name on Added “Features” heading above list of features on “Clock, Reset and Supply Management” on page Changed ...
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Table 30. Revision History Date Revision Section 15.2 DEVICE ORDERING - removed Table 26, “Supported Part Numbers” - added - added - added 20-Dec-2006 2 - added - added - added Updated option list on Changed a statement to indicate ...
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ST7L15, ST7L19 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this docu- ment, and the products and services described ...