ST7FL15F1MAE STMICROELECTRONICS [STMicroelectronics], ST7FL15F1MAE Datasheet - Page 22

• Manufacturer Part Number: ST7FL15F1MAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, data EEPROM, ADC, 5 timers, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7L15, ST7L19
SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d)
7.2 PHASE LOCKED LOOP
The PLL can be used to multiply a 1 MHz frequen-
cy from the RC oscillator or the external clock by 4
or 8 to obtain f
bled and the multiplication factor of 4 or 8 is select-
ed by 2 option bits:
– The x4 PLL is intended for operation with V
– The x8 PLL is intended for operation with V
Refer to
tion.
If the PLL is disabled and the RC oscillator is ena-
bled, then f
If both the RC oscillator and the PLL are disabled,
f
Figure 11. PLL Output Frequency Timing
Diagram
When the PLL is started, after reset or wake-up
from HALT mode or AWUFH mode, it outputs the
clock after a delay of t
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACC
a stabilization time of t
section 13.3.3 on page
Refer to
of the LOCKED bit in the SICSR register.
Note:
1. It is possible to obtain f
to 5.5V range with internal RC and PLL enabled by
selecting 1 MHz RC and x8 PLL and setting the
PLLdiv2 bit in the PLLTST register (see
7.6.3 on page
22/138
1
OSC
the 3V to 3.6V range (available only on Flash de-
vices)
the 3.6V to 5.5V range
4/8 x
input
freq.
is driven by the external clock.
t
STARTUP
section 7.6.3 on page 30
Section 15.1
OSC
30).
OSC
t
= 1 MHz.
LOCK
of 4 or 8 MHz. The PLL is ena-
STARTUP
for the option byte descrip-
105)
STAB
1)
OSC
LOCKED bit set
(see
t
PLL
= 4 MHz in the 3.3V
.
STAB
) is reached after
for a description
Figure 11
section
DD
DD
t
and
in
in
7.3 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by
hardware after a reset. This bit enables the MCO
output clock.
0: MCO clock disabled, I/O port free for general
1: MCO clock enabled.
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the input
clock f
0: Normal mode (f
1: Slow mode (f
RC CONTROL REGISTER (RCCR)
Read / Write
Reset Value: 1111 1111 (FFh)
Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad-
justment Bits
These bits must be written immediately after reset
to adjust the RC oscillator frequency and to obtain
an accuracy of 1%. The application can store the
correct value for each voltage range in EEPROM
and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
These bits are used with the CR[1:0] bits in the
SICSR register. Refer to
Note: To tune the oscillator, write a series of differ-
ent values in the register until the correct frequen-
cy is reached. The fastest method is to use a di-
chotomy starting with 80h.
CR9
purpose I/O.
7
0
7
OSC
CR8
0
or f
CR7
OSC
0
CPU =
/32.
CPU =
CR6
0
f
OSC
f
OSC
section 7.6.3 on page
CR5
/32)
0
)
CR4
0
MCO
CR3
CR2
SMS
0
0
30.