LPC2917/01 NXP [NXP Semiconductors], LPC2917/01 Datasheet - Page 56

• Manufacturer Part Number: LPC2917/01
• Description: ARM9 microcontroller with CAN and LIN
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC2917_19_01_2
Preliminary data sheet
6.16.1 Functional description
6.16 Vectored Interrupt Controller (VIC)
Table 31.
Legend:
‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored
‘+’ Indicates that the related register bit is readable and writable
The LPC2917/2919/01 contains a very flexible and powerful Vectored Interrupt Controller
to interrupt the ARM processor on request.
The key features are:
The Vectored Interrupt Controller routes incoming interrupt requests to the ARM
processor. The interrupt target is configured for each interrupt request input of the VIC.
The targets are defined as follows:
Interrupt-request masking is performed individually per interrupt target by comparing the
priority level assigned to a specific interrupt request with a target-specific priority
threshold. The priority levels are defined as follows:
Branch clock name
CLK_SPI2
CLK_TMR0
CLK_TMR1
CLK_TMR2
CLK_TMR3
CLK_ADC1
CLK_ADC2
•
•
•
•
•
•
•
•
•
•
•
•
Level-active interrupt request with programmable polarity.
56 interrupt-request inputs.
Software-interrupt request capability associated with each request input.
Interrupt request state can be observed before masking.
Software-programmable priority assignments to interrupt requests up to 15 levels.
Software-programmable routing of interrupt requests towards the ARM-processor
inputs IRQ and FIQ.
Fast identification of interrupt requests through vector.
Support for nesting of interrupt service routines.
Target 0 is ARM processor FIQ (fast interrupt service).
Target 1 is ARM processor IRQ (standard interrupt service).
Priority level 0 corresponds to ‘masked’ (i.e. interrupt requests with priority 0 never
lead to an interrupt).
Priority 1 corresponds to the lowest priority.
Branch clock overview
Rev. 02 — 17 June 2009
Base clock
BASE_SPI_CLK
BASE_TMR_CLK
BASE_TMR_CLK
BASE_TMR_CLK
BASE_TMR_CLK
BASE_ADC_CLK
BASE_ADC_CLK
…continued
LPC2917/01; LPC2919/01
ARM9 microcontroller with CAN and LIN
Implemented switch on/off
mechanism
WAKE-UP
+
+
+
+
+
+
+
AUTO
+
+
+
+
+
+
+
© NXP B.V. 2009. All rights reserved.
RUN
+
+
+
+
+
+
+
56 of 86