LPC2917/01 NXP [NXP Semiconductors], LPC2917/01 Datasheet - Page 40

• Manufacturer Part Number: LPC2917/01
• Description: ARM9 microcontroller with CAN and LIN
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC2917_19_01_2
Preliminary data sheet
Fig 9.
APB system bus
ADC block diagram
IRQ compare
6.14.4.1 Functional description
6.14.4.2 Pin description
IRQ scan
The ADC block diagram,
functionality is divided into two major parts; one part running on the MSCSS Subsystem
clock, the other on the ADC clock. This split into two clock domains affects the behavior
from a system-level perspective. The actual analog-to-digital conversions take place in the
ADC clock domain, but system control takes place in the system clock domain.
A mechanism is provided to modify configuration of the ADC and control the moment at
which the updated configuration is transferred to the ADC domain.
The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower than
or equal to the system clock frequency. To meet this constraint or to select the desired
lower sampling frequency, the clock generation unit provides a programmable fractional
system-clock divider dedicated to the ADC clock. Conversion rate is determined by the
ADC clock frequency divided by the number of resolution bits plus one. Accessing ADC
registers requires an enabled ADC clock, which is controllable via the clock generation
unit, see
Each ADC has four start inputs. Note that start 0 and start 2 are captured in the system
clock domain while start 1 and start 3 are captured in the ADC domain. The start inputs
are connected at MSCSS level, see
The two ADC modules in the MSCSS have the pins described below. The ADCx input pins
are combined with other functions on the port pins of the LPC2917/2919/01. The VREFN
and VREFP pins are common for both ADCs.
(BASE_MSCSS_CLK)
start 0
ADC
REGISTERS
APB clock
ADC
Section
start 2
ADC
SYSTEM DOMAIN
configuration data
conversion data
6.15.2.
update
IRQ
Rev. 02 — 17 June 2009
Figure
(BASE_ADC_CLK)
start 1
(up to 4.5 MHz)
ADC
CONTROL
ADC clock
9, shows the basic architecture of each ADC. The ADC
ADC
LPC2917/01; LPC2919/01
Figure 8
start 3
ADC
sync_out
for details.
Table 22
ARM9 microcontroller with CAN and LIN
ADC DOMAIN
ADC1
ADC2
3.3 V
3.3 V
shows the ADC pins.
ANALOG
ANALOG
3.3 V IN
3.3 V IN
MUX
MUX
© NXP B.V. 2009. All rights reserved.
ADC1 IN[7:0]
ADC2 IN[7:0]
002aad960
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