LPC2917/01 NXP [NXP Semiconductors], LPC2917/01 Datasheet - Page 53

• Manufacturer Part Number: LPC2917/01
• Description: ARM9 microcontroller with CAN and LIN
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC2917_19_01_2
Preliminary data sheet
6.15.4.2 Pin description
6.15.5 Power Management Unit (PMU)
Table 29.
The RGU module in the LPC2917/2919/01 has the following pins.
RGU pins.
Table 30.
This module enables software to actively control the system’s power consumption by
disabling clocks not required in a particular operating mode.
Reset output
POR_RST
RGU_RST
PCR_RST
COLD_RST
WARM_RST
SCU_RST
CFID_RST
FMC_RST
EMC_RST
SMC_RST
GESS_A2A_RST
PESS_A2A_RST
GPIO_RST
UART_RST
TMR_RST
SPI_RST
IVNSS_A2A_RST
IVNSS_CAN_RST
IVNSS_LIN_RST
MSCSS_A2A_RST
MSCSS_PWM_RST
MSCSS_ADC_RST
MSCSS_TMR_RST
I2C_RST
QEI_RST
DMA_RST
VIC_RST
AHB_RST
Symbol
RST
Reset output configuration
RGU pins
Direction
IN
Reset source
power-on reset module
POR_RST, RST pin
RGU_RST, WATCHDOG
PCR_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
Rev. 02 — 17 June 2009
Description
external reset input, Active LOW; pulled up internally
LPC2917/01; LPC2919/01
Parts of the device reset when activated
LP_OSC; is source for RGU_RST
RGU internal; is source for PCR_RST
PCR internal; is source for COLD_RST
parts with COLD_RST as reset source below
parts with WARM_RST as reset source below
SCU
CFID
embedded Flash-Memory Controller (FMC)
embedded SRAM-Memory Controller
external Static-Memory Controller (SMC)
GeSS AHB-to-APB bridge
PeSS AHB-to-APB bridge
all GPIO modules
all UART modules
all Timer modules in PeSS
all SPI modules
IVNSS AHB-to-APB bridge
all CAN modules including Acceptance filter
all LIN modules
MSCSS AHB to APB bridge
all PWM modules
all ADC modules
all Timer modules in MSCSS
all I2C modules
Quadrature encoder
GPDMA controller
Vectored Interrupt Controller (VIC)
CPU and AHB Bus infrastructure
ARM9 microcontroller with CAN and LIN
Table 30
© NXP B.V. 2009. All rights reserved.
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