ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 81

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

PCIFR – Pin Change Interrupt
Flag Register
PCMSK2 – Pin Change Mask
Register 2
PCMSK1 – Pin Change Mask
Register 1
2549K–AVR–01/07
• Bit 2 – PCIF2: Pin Change Interrupt Flag 1
When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2
becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
• Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1
becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0
becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16
Each PCINT23:16-bit selects whether pin change interrupt is enabled on the corre-
sponding I/O pin. If PCINT23:16 is set and the PCIE2 bit in PCICR is set, pin change
interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is cleared, pin change
interrupt on the corresponding I/O pin is disabled.
• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the correspond-
ing I/O pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on
the corresponding I/O pin is disabled.
Bit
0x1B (0x3B)
Read/Write
Initial Value
Bit
(0x6D)
Read/Write
Initial Value
Bit
(0x6C)
Read/Write
Initial Value
PCINT23
PCINT15
R/W
R/W
7
0
7
0
R
7
–
0
PCINT22
PCINT14
R/W
R/W
6
0
6
0
ATmega640/1280/1281/2560/2561
R
6
–
0
PCINT21
PCINT13
R/W
R/W
5
0
5
0
R
5
–
0
PCINT20
PCINT12
R/W
R/W
4
0
4
0
R
4
–
0
PCINT19
PCINT11
R/W
R/W
3
0
3
0
R
3
–
0
PCINT18
PCINT10
PCIF2
R/W
R/W
R/W
2
0
2
0
2
0
PCINT17
PCIF1
PCINT9
R/W
R/W
R/W
1
0
1
0
1
0
PCINT16
PCIF0
PCINT8
R/W
R/W
R/W
0
0
0
0
0
0
PCIFR
PCMSK2
PCMSK1
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