ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 27

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Address Latch Requirements
2549K–AVR–01/07
For details about the port override, see the alternate functions in section “I/O-Ports” on
page 83. The XMEM interface will auto-detect whether an access is internal or external.
If the access is external, the XMEM interface will output address, data, and the control
signals on the ports according to Figure 15 (this figure shows the wave forms without
wait-states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE is
low during a data transfer. When the XMEM interface is enabled, also an internal access
will cause activity on address, data and ALE ports, but the RD and WR strobes will not
toggle during internal access. When the External Memory Interface is disabled, the nor-
mal pin and data direction settings are used. Note that when the XMEM interface is
disabled, the address space above the internal SRAM boundary is not mapped into the
internal SRAM. Figure 14 illustrates how to connect an external SRAM to the AVR using
an octal latch (typically “74 x 573” or equivalent) which is transparent when G is high.
Due to the high-speed operation of the XRAM interface, the address latch must be
selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.
When operating at conditions above these frequencies, the typical old style 74HC series
latch becomes inadequate. The External Memory Interface is designed in compliance to
the 74AHC series latch. However, most latches can be used as long they comply with
the main timing parameters. The main parameters for the address latch are:
•
•
•
The External Memory Interface is designed to guaranty minimum address hold time
after G is asserted low of t
Timing” Tables 173 through Tables 180 on pages 385 - 387. The D-to-Q propagation
delay (t
ment of the external component. The data setup time before G low (t
exceed address valid to ALE low (t
capacitive load).
Figure 14. External SRAM Connected to the AVR
D to Q propagation delay (t
Data setup time before G low (t
Data (address) hold time after G low (
PD
) must be taken into consideration when calculating the access time require-
AVR
AD7:0
A15:8
ALE
ATmega640/1280/1281/2560/2561
WR
RD
h
= 5 ns. Refer to t
PD
).
SU
AVLLC
).
) minus PCB wiring delay (dependent on the
D
G
TH
).
LAXX_LD
Q
/t
LLAXX_ST
D[7:0]
A[7:0]
A[15:8]
RD
WR
SRAM
in “External Data Memory
SU
) must not
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