ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 248

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Data Packet Format
Combining Address and Data
Packets into a Transmission
Figure 95. Typical Data Transmission
248
SDA
SCL
START
ATmega640/1280/1281/2560/2561
Addr MSB
1
2
SLA+R/W
All data packets transmitted on the TWI bus are nine bits long, consisting of one data
byte and an acknowledge bit. During a data transfer, the Master generates the clock and
the START and STOP conditions, while the Receiver is responsible for acknowledging
the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line
low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is sig-
nalled. When the Receiver has received the last byte, or for some reason cannot receive
any more bytes, it should inform the Transmitter by sending a NACK after the final byte.
The MSB of the data byte is transmitted first.
Figure 94. Data Packet Format
A transmission basically consists of a START condition, a SLA+R/W, one or more data
packets and a STOP condition. An empty message, consisting of a START followed by
a STOP condition, is illegal. Note that the Wired-ANDing of the SCL line can be used to
implement handshaking between the Master and the Slave. The Slave can extend the
SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the
Master is too fast for the Slave, or the Slave needs extra time for processing between
the data transmissions. The Slave extending the SCL low period will not affect the SCL
high period, which is determined by the Master. As a consequence, the Slave can
reduce the TWI data transfer speed by prolonging the SCL duty cycle.
Figure 95 shows a typical data transmission. Note that several data bytes can be trans-
mitted between the SLA+R/W and the STOP condition, depending on the software
protocol implemented by the application software.
Transmitter
Aggregate
SDA from
SDA from
SCL from
Addr LSB
Receiver
Master
SDA
7
SLA+R/W
R/W
8
ACK
9
Data MSB
1
2
Data MSB
1
Data Byte
2
Data Byte
7
Data LSB
8
7
Data LSB
ACK
9
8
ACK
9
STOP, REPEATED
2549K–AVR–01/07
START or Next
Data Byte
STOP