ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 224

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Asynchronous Operational
Range
224
ATmega640/1280/1281/2560/2561
are emphasized on the figure by having the sample number inside boxes. The majority
voting process is done as follows: If two or all three samples have high levels, the
received bit is registered to be a logic 1. If two or all three samples have low levels, the
received bit is registered to be a logic 0. This majority voting process acts as a low pass
filter for the incoming signal on the RxDn pin. The recovery process is then repeated
until a complete frame is received. Including the first stop bit. Note that the Receiver only
uses the first stop bit of a frame.
Figure 88 shows the sampling of the stop bit and the earliest possible beginning of the
start bit of the next frame.
Figure 88. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If
the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after
the last of the bits used for majority voting. For Normal Speed mode, the first low level
sample can be at point marked (A) in Figure 88. For Double Speed mode the first low
level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detec-
tion influences the operational range of the Receiver.
The operational range of the Receiver is dependent on the mismatch between the
received bit rate and the internally generated baud rate. If the Transmitter is sending
frames at too fast or too slow bit rates, or the internally generated baud rate of the
Receiver does not have a similar (see Table 102) base frequency, the Receiver will not
be able to synchronize the frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and
internal receiver baud rate.
D
S
S
S
R
F
M
slow
(U2X = 0)
(U2X = 1)
Sample
Sample
RxD
Sum of character size and parity size (D = 5 to 10 bit)
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
mode.
First sample number used for majority voting. S
for Double Speed mode.
Middle sample number used for majority voting. S
S
is the ratio of the slowest incoming data rate that can be accepted in relation to the
receiver baud rate. R
accepted in relation to the receiver baud rate.
M
R
= 5 for Double Speed mode.
slow
=
------------------------------------------ -
S 1
1
1
–
(
2
D
+
+
D S ⋅
3
2
1
fast
)S
4
+
is the ratio of the fastest incoming data rate that can be
S
F
5
3
6
7
4
8
STOP 1
9
5
10
F
(A)
0/1
6
R
= 8 for normal speed and S
M
fast
0/1
= 9 for normal speed and
=
(B)
0/1
0/1
-----------------------------------
(
D
(
+
D
1
+
)S
2
)S
+
S
2549K–AVR–01/07
(C)
M
F
= 4