ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 22

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

EEPROM Data Memory
EEPROM Read/Write Access
22
ATmega640/1280/1281/2560/2561
The ATmega640/1280/1281/2560/2561 contains 4K bytes of data EEPROM memory. It
is organized as a separate data space, in which single bytes can be read and written.
The EEPROM has an endurance of at least 100,000 write/erase cycles. The access
between the EEPROM and the CPU is described in the following, specifying the
EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control
Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM,
see “Serial Downloading” on page 356, “Programming via the JTAG Interface” on page
361, and “Programming the EEPROM” on page 350 respectively.
The EEPROM Access Registers are accessible in the I/O space, see “Register Descrip-
tion” on page 32.
The write access time for the EEPROM is given in Table 5 on page 22. A self-timing
function, however, lets the user software detect when the next byte can be written. If the
user code contains instructions that write the EEPROM, some precautions must be
taken. In heavily filtered power supplies, V
up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. See “Preventing EEPROM Corrup-
tion” on page 24. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-
lowed. See the description of the EEPROM Control Register for details on this, “Register
Description” on page 32.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
The calibrated Oscillator is used to time the EEPROM accesses. Table 5 lists the typical
programming time for EEPROM access from the CPU.
Table 5. EEPROM Programming Time
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g. by disabling inter-
rupts globally) so that no interrupts will occur during execution of these functions. The
examples also assume that no Flash Boot Loader is present in the software. If such
code is present, the EEPROM write function must also wait for any ongoing SPM com-
mand to finish.
Symbol
EEPROM write
(from CPU)
Number of Calibrated RC Oscillator Cycles
26,368
CC
is likely to rise or fall slowly on power-
Typ Programming Time
3.3 ms
2549K–AVR–01/07